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ISP1581BD,518 参数 Datasheet PDF下载

ISP1581BD,518图片预览
型号: ISP1581BD,518
PDF下载: 下载PDF文件 查看货源
内容描述: [IC UNIVERSAL SERIAL BUS CONTROLLER, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64, Bus Controller]
分类和应用: 时钟数据传输外围集成电路
文件页数/大小: 80 页 / 389 K
品牌: NXP [ NXP ]
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ISP1581  
Hi-Speed USB peripheral controller  
Philips Semiconductors  
Table 4:  
Name  
Register overview…continued  
Destination  
Address  
(Hex)  
Description  
Size  
(bytes)  
DMA registers  
DMA Command  
DMA controller  
DMA controller  
DMA controller  
30  
controls all DMA transfers  
1
4
1
DMA Transfer Counter  
DMA Configuration  
34  
sets byte count for DMA Transfer  
38 (byte 0)  
sets GDMA configuration (counter enable,  
burst length, data strobing, bus width)  
39 (byte 1)  
sets ATA configuration (IORDY enable,  
mode selection: ATA/UDMA/MDMA/PIO)  
1
1
2
DMA Hardware  
1F0 Task File  
DMA controller  
3C  
40  
endian type, master/slave selection, signal  
polarity for DACK, DREQ, DIOW, DIOR  
ATAPI peripheral  
single address word register: byte 0 (lower  
byte) is accessed first  
1F1Task File  
1F2 Task File  
1F3 Task File  
1F4 Task File  
1F5 Task File  
1F6 Task File  
1F7 Task File  
ATAPI peripheral  
ATAPI peripheral  
ATAPI peripheral  
ATAPI peripheral  
ATAPI peripheral  
ATAPI peripheral  
ATAPI peripheral  
48  
49  
4A  
4B  
4C  
4D  
44  
IDE device access  
IDE device access  
IDE device access  
IDE device access  
IDE device access  
IDE device access  
1
1
1
1
1
1
1
IDE device access (write only; reading  
returns FFH)  
3F6 Task File  
ATAPI peripheral  
ATAPI peripheral  
DMA controller  
4E  
IDE device access  
1
1
1
1
1
1
1
1
3F7 Task File  
4F  
IDE device access  
DMA Interrupt Reason  
50 (byte 0)  
51 (byte 1)  
54 (byte 0)  
55 (byte 1)  
58  
shows reason (source) for DMA interrupt  
DMA Interrupt Enable  
DMA controller  
enables DMA interrupt sources  
DMA Endpoint  
DMA Strobe Timing  
General registers  
Interrupt  
DMA controller  
DMA controller  
selects endpoint FIFO, data flow direction  
strobe duration in UDMA/MDMA mode  
60  
device  
device  
device  
18  
70  
74  
shows interrupt sources  
4
3
2
Chip ID  
product ID code and hardware version  
Frame Number  
last successfully received Start Of Frame:  
lower byte (byte 0) is accessed first  
Scratch  
device  
PHY  
78  
84  
allows save/restore of firmware status  
during ‘suspend’  
2
1
Test Mode  
direct setting of D+, Dstates, internal  
transceiver test (PHY)  
9397 750 13462  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 06 — 23 December 2004  
17 of 79  
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