ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
Table 13: Interrupt Enable register: bit description…continued
Bit
6
Symbol
IEDMA
Description
A logic 1 enables interrupt upon DMA status change detection.
5
IEHS_STA
A logic 1 enables interrupt upon detection of a High Speed
Status change.
4
3
2
1
0
IERESM
IESUSP
IEPSOF
IESOF
A logic 1 enables interrupt upon detection of a ‘resume’ state.
A logic 1 enables interrupt upon detection of a ‘suspend’ state.
A logic 1 enables interrupt upon detection of a Pseudo SOF.
A logic 1 enables interrupt upon detection of an SOF.
IEBRST
A logic 1 enables interrupt upon detection of a bus reset.
9.2.5 DMA Configuration register (address: 38H)
See Section 9.4.3.
9.2.6 DMA Hardware register (address: 3CH)
See Section 9.4.4.
9.3 Data flow registers
9.3.1 Endpoint Index register (address: 2CH)
The Endpoint Index register selects a target endpoint for register access by the
microcontroller. The register consists of 1 byte and the bit allocation is shown in
Table 14. The following registers are indexed:
• Endpoint MaxPacketSize
• Endpoint Type
• Buffer Length
• Data Port
• Short Packet
• Control Function.
For example, to access the OUT data buffer of endpoint 1 via the Data Port register,
the Endpoint Index register has to be written first with 02H.
Table 14: Endpoint Index register: bit allocation
Bit
7
6
5
4
3
2
1
0
DIR
0
Symbol
Reset
reserved
EP0SETUP
0
ENDPIDX[3:0]
00H
-
-
Bus reset
Access
unchanged
R/W
R/W
R/W
R/W
R/W
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
22 of 79
NXP [ NXP ]
