ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
Bit
7
6
5
4
3
2
1
0
Symbol
IE_1F0_
WF_E
IE_1F0_
WF_F
IE_1F0_
RF_E
IE_
READ_1F0
IE_BSY_
DONE
IE_TF_
RD_DONE INTRQ_OK
IE_CMD_
reserved
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
Bus reset
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
9.4.9 DMA Endpoint register (address: 58H)
This 1-byte register selects a USB endpoint FIFO as a source or destination for DMA
transfers. The bit allocation is given in Table 55.
Table 55: DMA Endpoint register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Power Reset
Bus Reset
Access
reserved
EPIDX[2:0]
DMADIR
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 56: DMA Endpoint register: bit description
Bit
Symbol
-
Description
7 to 4
3 to 1
0
reserved
EPIDX[2:0]
DMADIR
selects the indicated endpoint for DMA access
0 — selects the RX/OUT FIFO for DMA read transfers
1 — selects the TX/IN FIFO for DMA write transfers.
The DMA Endpoint register must not reference the endpoint that is indexed by the
Endpoint Index register (02CH) at any time. Doing so would result in data corruption.
Therefore, if the DMA Endpoint register is unused, point it to an unused endpoint.
However, if the DMA Endpoint register is pointed to an active endpoint, the firmware
must not reference the same endpoint on the Endpoint Index register.
9.5 General registers
9.5.1 Interrupt register (address: 18H)
The Interrupt register consists of 4 bytes. The bit allocation is given in Table 57.
When a bit is set in the Interrupt register, this indicates that the hardware condition for
an interrupt has occurred. When the Interrupt register content is non-zero, the INT
output will be asserted. Upon detecting the interrupt, the external microprocessor
must read the Interrupt register to determine the source of the interrupt.
Each endpoint buffer has a dedicated interrupt bit (EPnTX, EPnRX). In addition,
various bus states can generate an interrupt: Resume, Suspend, Pseudo-SOF, SOF
and Bus Reset. The DMA Controller only has one interrupt bit: the source for a DMA
interrupt is shown in the DMA Interrupt Reason register (see Table 51).
Each interrupt bit can be individually cleared by writing a logic 1. The DMA interrupt
bit can be cleared by writing a logic 1 to the related interrupt source bit in the DMA
Interrupt Reason register and writing a logic 1 to the DMA bit of the interrupt register.
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
42 of 79
NXP [ NXP ]
