ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
Table 60: Chip ID Register: bit description
Bit
Symbol
Description
23 to 16
15 to 8
7 to 0
CHIPID[23:16] Chip ID: lower byte (15H)
CHIPID[15:8] Chip ID: upper byte (81H)
VERSION
Version number (51H): The version number will be upgraded as
and when there are new revisions with improved performance
and functionality.
9.5.3 Frame Number register (address: 74H)
This read-only register contains the frame number of the last successfully received
Start Of Frame (SOF). The register contains 2 bytes and the bit allocation is given in
Table 61. In case of 8-bit access the register content is returned lower byte first.
Table 61: Frame Number register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
Power Reset
Bus Reset
Access
reserved
MICROSOF[2:0]
SOFR[10:8]
-
-
-
-
00H
00H
R
00H
00H
R
R
7
R
6
Bit
5
4
3
2
1
0
Symbol
Power Reset
Bus Reset
Access
SOFR[7:0]
00H
00H
R
Table 62: Frame Number register: bit description
Bit
Symbol
MICROSOF[2:0] microframe number
SOFR[10:0] frame number
Description
13 to 11
10 to 0
9.5.4 Scratch register (address: 78H)
This 16-bit register can be used by the firmware to save and restore information, for
example, the device status before it enters ‘suspend’ state. The bit allocation is given
in Table 63.
Table 63: Scratch Register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
Reset
SFIRH[7:0]
00H
Bus reset
Access
Bit
00H
R/W
7
6
5
4
3
2
1
0
Symbol
Reset
SFIRL[7:0]
00H
Bus reset
Access
00H
R/W
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
45 of 79
NXP [ NXP ]
