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ISP1581BD,551 参数 Datasheet PDF下载

ISP1581BD,551图片预览
型号: ISP1581BD,551
PDF下载: 下载PDF文件 查看货源
内容描述: [IC UNIVERSAL SERIAL BUS CONTROLLER, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64, Bus Controller]
分类和应用: 时钟数据传输外围集成电路
文件页数/大小: 80 页 / 389 K
品牌: NXP [ NXP ]
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ISP1581  
Hi-Speed USB peripheral controller  
Philips Semiconductors  
Table 64: Scratch Information register: bit description  
Bit  
Symbol  
Description  
15 to 8  
7 to 0  
SFIRH[7:0]  
SFIRL[7:0]  
scratch firmware information register (high byte)  
scratch firmware information register (low byte)  
9.5.5 Test Mode register (address: 84H)  
This 1-byte register allows the firmware to set the (D+, D−) lines to predetermined  
states for testing purposes. The bit allocation is given in Table 65.  
Remark: Only one bit can be set at a time.  
Table 65: Test Mode register: bit allocation  
Bit  
7
6
5
4
3
PRBS  
0
2
1
JSTATE  
0
0
Symbol  
Reset  
FORCEHS  
reserved  
FORCEFS  
KSTATE  
SE0_NAK  
0
0
-
-
-
-
0
0
0
0
0
0
Bus reset  
Access  
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Table 66: Test Mode Register: bit description  
Bit  
Symbol  
Description  
7[1]  
FORCEHS  
A logic 1 forces the hardware to high-speed mode only and  
disables the chirp detection logic.  
6 to 5  
4[1]  
-
reserved.  
FORCEFS  
A logic 1 forces the physical layer to full-speed mode only and  
disables the chirp detection logic.  
3[2]  
PRBS  
A logic 1 sets the (D+, D) lines to toggle in a pre-determined  
random pattern.  
2[2]  
1[2]  
0[2]  
KSTATE  
JSTATE  
Writing a logic 1 sets the (D+, D) lines to the K state.  
Writing a logic 1 sets the (D+, D) lines to the J state.  
SE0_NAK  
Writing a logic 1 sets the (D+, D) lines to a HS quiescent state.  
The device only responds to a valid HS IN token with a NAK.  
[1] Either FORCEHS or FORCEFS should be set to logic 1 at a time.  
[2] Of the four bits (PRBS, KSTATE, JSTATE and SE0_NAK), only one bit must be set to logic 1 at a  
time.  
10. Power supply  
The ISP1581 can be powered from 3.3 V or 5.0 V.  
If the ISP1581 is powered from VCC = 5.0 V, an integrated voltage regulator provides  
a 3.3 V supply voltage for the internal logic and the USB transceiver. For connection  
details, see Figure 6.  
The ISP1581 can also be operated from VCC = 3.3 V. In this case, the internal  
regulator is disabled and all the supply pins are connected to VCC. For connection  
details see Figure 7.  
9397 750 13462  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 06 — 23 December 2004  
46 of 79  
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