ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
Table 40: ATAPI peripheral register addressing
Task file
CS1
H
CS0
L
DA2
L
DA1
L
DA0
L
1F0
1F1
1F2
1F3
1F4
1F5
1F6
1F7
3F6
3F7
H
L
L
L
H
L
H
L
L
H
H
L
H
L
L
H
L
H
L
H
H
H
H
H
H
H
L
L
H
L
H
L
H
H
H
H
H
L
H
L
L
H
H
L
H
In 8-bit bus mode, the 16-bit Task File register 1F0 requires 2 consecutive write/read
accesses before the proper PIO write/read is generated on the IDE interface. The first
byte is always the lower byte (LSByte). Other task file registers can be accessed
directly.
Writing to Task File registers can be done in any order except for Task File register
1F7, which must be written last.
Table 41: Task File register 1F0 (address: 40H): bit allocation
CS1 = H, CS0 = L, DA2 = L, DA1 = L, DA0 = L.
Bit
7
6
5
4
3
2
1
0
0
0
Symbol
Reset
data (ATA or ATAPI)
00H
00H
R/W
Bus reset
Access
Table 42: Task File register 1F1 (address: 48H): bit allocation
CS1 = H, CS0 = L, DA2 = L, DA1 = L, DA0 = H.
Bit
7
6
5
4
3
2
1
Symbol
Reset
error/feature (ATA or ATAPI)
00H
00H
R/W
Bus reset
Access
Table 43: Task File register 1F2 (address: 49H): bit allocation
CS1 = H, CS0 = L, DA2 = L, DA1 = H, DA0 = L.
Bit
7
6
5
4
3
2
1
Symbol
Reset
sector count (ATA) or interrupt reason (ATAPI)
00H
00H
R/W
Bus reset
Access
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
38 of 79
NXP [ NXP ]
