ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
Table 34: DMA Configuration register: bit description
Bit[1]
Symbol
Description
15
14
13
-
reserved
IGNORE_IORDY
ATA_MODE
A logic 1 ignores the IORDY input signal (UDMA mode only).
A logic 1 configures the DMA core for ATA or MDMA mode.
Used when issuing DMA commands 02H to 07H, 0AH and
0CH; also used when directly accessing task file registers.
A logic 0 configures the DMA core for non-ATA mode. Used
when issuing DMA commands 00H and 01H.
12 to 11 DMA_MODE[1:0]
These bits affect the timing for UDMA and MDMA mode:
00H — UDMA/MDMA mode 0: ATA(PI) compatible timings
01H — UDMA/MDMA mode 1: ATA(PI) compatible timings
02H — UDMA/MDMA mode 2: ATA(PI) compatible timings
03H — MDMA mode 3: enables the DMA Strobe Timing
register (see Table 37 and Table 38) for non-standard strobe
durations; only used in MDMA mode.
10 to 8 PIO_MODE[2:0][4] These bits affect the PIO timing (see Table 77):
00H to 04H — PIO mode 0 to 4: ATA(PI) compatible timings
05H to 07H — reserved.
7
DIS_XFER_CNT
BURST[2:0]
A logic 1 disables the DMA Transfer Counter (see Table 31).
The transfer counter can only be disabled in GDMA slave
mode; in master mode the counter is always enabled.
6 to 4
These bits select the DMA burst length and the DREQ timing
(GDMA Slave mode only):
00H — DREQ is asserted until the last byte/word is
transferred or until the FIFO becomes full or empty
01H — DREQ is asserted and negated for each byte/word
transferred[2][3]
02H — DREQ is asserted and negated for every
2 bytes/words transferred[2][3]
03H — DREQ is asserted and negated for every
4 bytes/words transferred[2][3]
04H — DREQ is asserted and negated for every
8 bytes/words transferred[2][3]
05H — DREQ is asserted and negated for every
12 bytes/words transferred[2][3]
06H — DREQ is asserted and negated for every
16 bytes/words transferred[2][3]
07H — DREQ is asserted and negated for every
32 bytes/words transferred[2][3]
.
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
34 of 79
NXP [ NXP ]
