ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
Bit
15
14
13
12
11
10
9
8
Symbol
Reset
DMACR2 = DMACR[15:8]
00H
00H
R/W
Bus reset
Access
Bit
7
6
5
4
3
2
1
0
Symbol
Reset
DMACR1 = DMACR[7:0]
00H
00H
R/W
Bus reset
Access
Table 32: DMA Transfer Counter register: bit description
Bit
Symbol
Description
31 to 24
DMACR4,
DMA transfer counter byte 4 (MSB)
DMACR[31:24]
23 to 16
15 to 8
7 to 0
DMACR3,
DMACR[23:16]
DMA transfer counter byte 3
DMA transfer counter byte 2
DMA transfer counter byte 1 (LSB)
DMACR2,
DMACR[15:8]
DMACR1,
DMACR[7:0]
9.4.3 DMA Configuration register (address: 38H)
This register defines the DMA configuration for the Generic DMA (GDMA) and the
Ultra-DMA (UDMA) modes. The DMA Configuration register consists of 2 bytes. The
bit allocation is given in Table 33.
Table 33: DMA Configuration register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
IGNORE_
IORDY
ATA_
MODE
DMA_MODE[1:0]
PIO_MODE[2:0]
Reset
-
-
0
0
0
00H
00H
R/W
00H
00H
Bus Reset
Access
Bit
0
R/W
R/W
7
R/W
6
R/W
5
4
3
2
1
0
Symbol
DIS_
XFER_
CNT
BURST[2:0]
MODE[1:0]
reserved
WIDTH
Reset
0
0
00H
00H
R/W
00H
00H
R/W
-
-
1
1
Bus Reset
Access
R/W
R/W
R/W
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
33 of 79
NXP [ NXP ]
