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ISP1581BD,551 参数 Datasheet PDF下载

ISP1581BD,551图片预览
型号: ISP1581BD,551
PDF下载: 下载PDF文件 查看货源
内容描述: [IC UNIVERSAL SERIAL BUS CONTROLLER, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64, Bus Controller]
分类和应用: 时钟数据传输外围集成电路
文件页数/大小: 80 页 / 389 K
品牌: NXP [ NXP ]
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ISP1581  
Hi-Speed USB peripheral controller  
Philips Semiconductors  
9.3.6 Endpoint Type register (address: 08H)  
This register sets the Endpoint type of the indexed endpoint: isochronous, bulk or  
interrupt. It also serves to enable the endpoint and configure it for double buffering.  
Automatic generation of an empty packet for a zero length TX buffer can be disabled  
via bit NOEMPKT. The register contains 2 bytes and the bit allocation is shown in  
Table 24.  
Table 24: Endpoint Type register: bit allocation  
Bit  
15  
14  
13  
12  
11  
10  
9
8
Symbol  
Reset  
reserved  
R/W  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bus reset  
Access  
Bit  
7
6
5
4
3
2
1
0
ENDPTYP[1:0]  
00H  
Symbol  
Reset  
reserved  
NOEMPKT  
ENABLE  
DBLBUF  
-
-
-
-
-
-
0
0
0
0
0
0
Bus reset  
Access  
00H  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Table 25: Endpoint Type register: bit description  
Bit  
Symbol  
Description  
15 to 5 reserved  
reserved.  
4
3
NOEMPKT  
ENABLE  
No Empty Packet: A logic 0 causes an empty packet to be  
appended to the next IN token of the USB data, if the Buffer  
Length register or the Endpoint MaxPacketSize register is zero.  
A logic 1 disables this function. This bit is applicable only in  
DMA mode.  
Endpoint Enable: A logic 1 enables the FIFO of the indexed  
endpoint. The memory size is allocated as specified in the  
Endpoint MaxPacketSize register. A logic 0 disables the FIFO.  
Note: ‘Stalling’ a data endpoint will confuse the Data Toggle bit  
on the stalled endpoint because the internal logic picks up from  
where it has stalled. Therefore, the Data Toggle bit must be  
reset by disabling and re-enabling the corresponding endpoint  
(by setting the bit ‘ENABLE’ to 0 or 1 in the endpoint type  
register) to reset the PID.  
2
DBLBUF  
Double Buffering: A logic 1 enables double buffering for the  
indexed endpoint. A logic 0 disables double buffering.  
1 to 0  
ENDPTYP[1:0]  
Endpoint Type: These bits select the endpoint type as follows:  
01H — isochronous  
02H — bulk  
03H — interrupt.  
9.3.7 Short Packet register (address: 24H)  
This register is reserved.  
9397 750 13462  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 06 — 23 December 2004  
27 of 79  
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