ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
Table 21: Buffer Length register: bit allocation
Bit
15
14
13
12
11
10
9
1
8
0
Symbol
Reset
DATACOUNT[15:8]
00H
00H
R/W
Bus reset
Access
Bit
7
6
5
4
3
2
Symbol
Reset
DATACOUNT[7:0]
00H
00H
R/W
Bus reset
Access
9.3.5 Endpoint MaxPacketSize register (address: 04H)
This register determines the maximum packet size for all endpoints except Control 0.
The register contains 2 bytes and the bit allocation is given in Table 22.
Each time the register is written, the Buffer Length registers of all endpoints are
re-initialized to the FFOSZ field value. The NTRANS bits control the number of
transactions allowed in a single micro-frame (for high-speed Isochronous and
interrupt endpoints only).
Table 22: Endpoint MaxPacketSize register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
Reset
reserved
NTRANS[1:0]
FFOSZ[10:8]
-
-
-
-
-
-
00H
00H
R/W
00H
00H
R/W
1
Bus reset
Access
Bit
R/W
7
R/W
6
R/W
5
4
3
2
0
Symbol
Reset
FFOSZ[7:0]
00H
Bus reset
Access
00H
R/W
Table 23: Endpoint MaxPacketSize register: bit description
Bit
Symbol
Description
15 to 13
12 to 11
reserved
reserved
NTRANS[1:0] Number of Transactions (HS mode only):
0 — 1 packet per microframe
1 — 2 packets per microframe
2 — 3 packets per microframe
3 — reserved.
These bits are applicable for Isochronous/interrupt transactions
only.
10 to 0
FFOSZ[10:0] FIFO Size: Sets the FIFO size in bytes for the indexed endpoint.
Applies to both HS and FS operation.
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
26 of 79
NXP [ NXP ]
