ISP1362
Single-chip USB OTG controller
Philips Semiconductors
15. HC registers
The HC contains a set of on-chip control registers. These registers can be read or
written by the HC Driver (HCD). The Control and Status register set, the Frame
Counter register set and the Root Hub register set are grouped under the category of
HC operational registers (32 bits). These operational registers are made compatible
to Open Host Controller Interface (OpenHCI) operational registers. This enables the
OpenHCI HCD to be ported easily to the ISP1362.
Reserved bits may be defined in future releases of this specification. To ensure
interoperability, the HCD that does not use a reserved field must not assume that the
reserved field contains logic 0. Furthermore, the HCD must always preserve the
values of the reserved field. When a R/W register is modified, the HCD must first read
the register, modify the desired bits and then write the register with the reserved bits
still containing the read value. Alternatively, the HCD can maintain an in-memory
copy of previously written values that can be modified and then written to the
HC register. When there is a write to set or clear the register, bits written to reserved
fields must be logic 0.
As shown in Table 34, the offset locations (the commands for reading registers) of
these operational registers (32-bit registers) are similar to those defined in the OHCI
specification. The addresses, however, are equal to offset divided by 4.
Table 34: HC Control registers summary
Command (Hex)
Register
Width Reference
Functionality
Read
00
01
02
03
04
05
0D
0E
0F
11
12
13
14
15
16
20
21
22
24
25
Write
N/A
81
HcRevision
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
16
16
16
16
16
Section 15.1.1 on page 71 HC Control and Status
registers
HcControl
Section 15.1.2 on page 71
82
HcCommandStatus
HcInterruptStatus
HcInterruptEnable
HcInterruptDisable
HcFmInterval
Section 15.1.3 on page 73
83
Section 15.1.4 on page 74
84
Section 15.1.5 on page 75
85
Section 15.1.6 on page 76
8D
8E
8F
91
Section 15.2.1 on page 78 HC Frame Counter
registers
HcFmRemaining
HcFmNumber
Section 15.2.2 on page 79
Section 15.2.3 on page 80
HcLSThreshold
HcRhDescriptorA
HcRhDescriptorB
HcRhStatus
Section 15.2.4 on page 81
92
Section 15.3.1 on page 82 HC Root Hub registers
Section 15.3.2 on page 84
93
94
Section 15.3.3 on page 85
95
HcRhPortStatus[1]
HcRhPortStatus[2]
HcHardwareConfiguration
HcDMAConfiguration
HcTransferCounter
HcµPInterrupt
Section 15.3.4 on page 87
96
Section 15.3.4 on page 87
A0
A1
A2
A4
A5
Section 15.4.1 on page 92 HC DMA and Interrupt
Control registers
Section 15.4.2 on page 94
Section 15.4.3 on page 95
Section 15.4.4 on page 95
Section 15.4.5 on page 97
HcµPInterruptEnable
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
69 of 150
NXP [ NXP ]
