ISP1362
Single-chip USB OTG controller
Philips Semiconductors
14.4 OtgInterruptEnable register (R/W: 69H/E9H)
Code (Hex): 69 — read
Code (Hex): E9 — write
Table 28: OtgInterruptEnable register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
OTG_
TMR_IE
B_SE0_
SRP_IE
A_SRP_
DET_IE
Reset
Access
Bit
-
-
-
-
-
-
-
-
0
R/W
2
0
R/W
1
0
R/W
0
-
7
-
6
5
4
3
Symbol
OTG_
OTG_
RMT_
CONN_IE
B_SESS_
VLD_IE
A_SESS_
VLD_IE
B_SESS_
END_IE
A_VBUS_
VLD_IE
ID_REG_
IE
RESUME_ SUSPND_
IE
IE
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 29: OtgInterruptEnable register: bit description
Bit
Symbol
Description
15 to 11
10
-
reserved
OTG_
Logic 1 enables interrupt when the OTG timer attains time-out.
TMR_IE
9
8
7
B_SE0_
SRP_IE
Logic 1 enables interrupt upon detection of the B_SE0_SRP status
change.
A_SRP_
DET_IE
Logic 1 enables interrupt upon detection of the SRP event.
OTG_
Logic 1 enables interrupt upon detection of bus resume (J to K
RESUME_ only) event.
IE
6
OTG_
Logic 1 enables interrupt upon detection of the bus ‘suspend’
SUSPND_ status change.
IE
5
4
3
2
1
0
RMT_
CONN_IE
Logic 1 enables interrupt upon detection of the RMT_CONN status
change.
B_SESS_
VLD_IE
Logic 1 enables interrupt upon detection of B_SESS_VLD status
change.
A_SESS_
VLD_IE
Logic 1 enables interrupt upon detection of A_SESS_VLD status
change.
B_SESS_
END_IE
Logic 1 enables interrupt upon detection of B_SESS_END status
change.
A_VBUS_
VLD_IE
Logic 1 enables interrupt upon detection of A_VBUS_VLD status
change.
ID_REG_IE Logic 1 enables interrupt upon detection of the ID_REG status
change.
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
66 of 150
NXP [ NXP ]
