ISP1362
Single-chip USB OTG controller
Philips Semiconductors
Table 26: OtgInterrupt register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
OTG_TMR
_TIMEOUT
B_SE0_
SRP
A_SRP_
DET
Reset
Access
Bit
-
-
-
-
-
-
-
-
-
-
0
R/W
2
0
R/W
1
0
R/W
0
7
6
5
4
3
Symbol
OTG_
RESUME
OTG_
SUSPND
RMT_
CONN_C
B_SESS_
VLD_C
A_SESS_
VLD_C
B_SESS_
END_C
A_VBUS_ ID_REG_C
VLD_C
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 27: OtgInterrupt register: bit description
Bit
Symbol
Description
15 to 11
10
-
reserved
OTG_TMR_ This bit is set whenever the OTG timer attains time-out. Writing
TIMEOUT
logic 1 clears this bit. Writing logic 0 has no effect.
0 — no event
1 — OTG Timer time-out
9
8
B_SE0_
SRP
This bit is set whenever the device detects more than 2 ms of SE0.
Writing logic 1 clears this bit. Writing logic 0 has no effect.
0 — no event
1 — bus has been in SE0 for more than 2 ms
A_SRP_
DET
This bit is used to detect the session request event (SRP) from the
remote device. The SRP event can be either VBUS pulsing or data
line pulsing. Bit 9 (A_SEL_SRP) of the OtgControl register
determines which SRP is selected. Writing logic 1 clears this bit.
Writing logic 0 has no effect.
0 — no event
1 — SRP is detected
7
OTG_
RESUME
This bit is used to detect a J to K state change when the device is
in the ‘suspend’ state. Writing logic 1 clears this bit. Writing logic 0
has no effect.
0 — no event
1 — a resume signal (J → K) is detected when the bus is in the
‘suspend’ state
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
64 of 150
NXP [ NXP ]
