ISP1362
Single-chip USB OTG controller
Philips Semiconductors
13. USB Device Controller (DC)
The design of the DC in the ISP1362 is compatible with the Philips ISP1181B USB
full-speed interface device IC. The functionality of the DC in the ISP1362 is similar to
the ISP1181B in the 16-bit bus mode. In addition, the command and register sets are
also the same.
In general, the DC in the ISP1362 provides 16 endpoints for the USB device
implementation. Each endpoint can be allocated RAM space in the on-chip ping pong
buffer RAM.
Remark: The ping pong buffer RAM for the DC is independent of the buffer RAM for
the Host Controller (HC). When the buffer RAM is full, the DC transfers the data in the
buffer RAM to the USB bus. When the buffer RAM is empty, an interrupt is generated
to notify the microprocessor to feed in data. The transfer of data between a
microprocessor and the DC can be done in either the Programmed I/O (PIO) mode or
in the direct memory access (DMA) mode.
13.1 DC data transfer operation
The following sessions explains how the DC in the ISP1362 handles an IN data
transfer and an OUT data transfer. An IN data transfer means transfer from the
ISP1362 to an external USB host (through the upstream port), and an OUT transfer
means transfer from an external USB host to the ISP1362. In the device mode, the
ISP1362 acts as a USB device.
13.1.1 IN data transfer
• The arrival of the IN token is detected by the Serial Interface Engine (SIE) by
decoding the Packet IDentifier (PID).
• The SIE also checks the device number and the endpoint number to verify whether
they are okay.
• If the endpoint is enabled, the SIE checks the contents of the DcEndpointStatus
register (ESR). If the endpoint is full, the contents of the buffer memory are sent
during the data phase else an NAK handshake is sent.
• After the data phase, the SIE expects a handshake (ACK) from the host (except for
ISO endpoints).
• On receiving the handshake (ACK), the SIE updates the contents of the
DcEndpointStatus and DcInterrupt registers, which in turn generates an interrupt
to the microprocessor. For ISO endpoints, the DcInterrupt register is updated as
soon as data is sent because there is no handshake phase.
• On receiving an interrupt, the microprocessor reads the DcInterrupt register. It will
know which endpoint has generated the interrupt and reads the contents of the
corresponding ESR. If the buffer is empty, it fills up the buffer so that data can be
sent by the SIE at the next IN token phase.
13.1.2 OUT data transfer
• The arrival of the OUT token is detected by the SIE by decoding the PID.
• The SIE checks the device and endpoint numbers to verify whether they are okay.
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
50 of 150
NXP [ NXP ]
