ISP1362
Single-chip USB OTG controller
Philips Semiconductors
H_OCn
FB2
V
BUS
(1)
C41
C17
0.1 µF
1
2
3
4
5
6
DGND
DGND
V
BUS
DM
DP
GND
chassis
chassis
n.c.
H_PSWn
004aaa150
DGND
(1) 100 µF for the host port or 4.7 µF for the OTG port.
Fig 25. Using internal charge pump.
12.8.4 OC detection circuit using external 5 V power source in the OTG mode
In the OTG mode using external 5 V power source for VBUS, the circuit and the
operation are the same as that for the non-OTG mode (see Section 12.8.1 and
Section 12.8.2).
12.9 ISP1362 HC Power Management
In the ISP1362, the HC and the DC are suspended and waken up individually. The
H_SUSPEND/H_WAKEUP and D_SUSPEND/D_WAKEUP pins must be pulled-up
by a large resistor (100 kΩ). In the suspend state, these pins are HIGH. To wake up
the HC, these pins must be pulled LOW.
The ISP1362 can be partially suspended (only the HC or only the DC). In the partially
suspended state, clock circuit and PLL continue to work. To save power, both the HC
and the DC must be set to the suspend mode.
The HC can be suspended by writing 0x06C0 to the HcControl register.
The HC can be set awake by one of the following ways:
• LOW pulse on the H_SUSPEND/H_WAKEUP pin, minimum length of pulse is
25 ns.
• LOW pulse on the chip select (CS) pin, minimum length of pulse is 25 ns.
• Resume signal by USB devices connected to the downstream port.
On waking up from the suspend state, the clock to the HC will sustain for 5 ms. Within
this 5 ms, the HC Driver must set the HC to the operational mode by writing 0x0680
to the HcControl register. If the HcControl register remains in the suspend state
(0x06C0) after waking up the HC, the HC will return to the suspend state after 5 ms.
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
49 of 150
NXP [ NXP ]
