ISP1362
Single-chip USB OTG controller
Philips Semiconductors
external OC detection circuit, set AnalogOCEnable, bit 10 of register
HcHardwareConfiguration, to logic 0. By default after reset this bit is set to logic 0.
Therefore, the HC Driver does not need to clear this bit.
Figure 24 shows how to use an external OC detection circuit.
OC DETECTION
PSU_5V
V
V
OC
H_OCn
IN
FB2
EN
H_PSWn
OUT
(1)
C41
C17
0.1 µF
1
2
3
4
5
6
DGND
DGND
V
BUS
DM
DP
GND
chassis
chassis
004aaa149
DGND
(1) 100 µF for the host port or 4.7 µF for the OTG port.
Fig 24. Using external OC detection circuit.
12.8.3 OC detection circuit using internal charge pump in the OTG mode
When port 1 is operating in the OTG mode, you may choose to use the internal
charge pump to provide 5 V VBUS, or supply VBUS from an external source. In this
mode, the overcurrent condition is detected by a drop in VBUS that will be sensed by
the built-in comparator. The overcurrent condition causes a change in the
A_VBUS_VLD bit of the OtgStatus register. The software has to clear the
DRV_VBUS bit in the OtgControl register when it detects the A_VBUS_VLD bit
turning to logic 0.
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
48 of 150
NXP [ NXP ]
