ISP1362
Single-chip USB OTG controller
Philips Semiconductors
Starting address of the
ATL or INTL buffer area
8 bytes PTD header
Block of 72 bytes
64 bytes PTD header
Payload area
(64 + 8,
where 64 is the block size defined)
8 bytes PTD header
72 bytes
64 bytes PTD header
Payload area
8 bytes PTD header
72 bytes
64 bytes PTD header
Payload area
004aaa055
Fig 5. A sample snapshot of the ATL or INTL memory management scheme.
Figure 5 provides a snapshot of a sample ATL or INTL buffer area of 256 bytes with a
block size of 64 bytes. The HCD may put a PTD with payload size of up to 64 bytes
but not more. Depending on the ATL or INTL buffer size, up to 32 ATL blocks and
32 INTL blocks can be allocated. Note that a portion of the ATL or INTL buffer
remains unused. This is allowed but can be avoided by choosing the appropriate ATL
or INTL buffer size and block size.
The ISTL0 or ISTL1 buffer memory (for isochronous transfer) uses a different
memory management scheme (see Figure 6). There is no fixed block size for the
ISTL buffer memory. While the PTD header remains 8 bytes for all PTDs, the PTD
payload can be of any size. The PTD payload, however, is padded to the next DWord
boundary when the HC calculates the location of the next PTD header. The
ISP1362 HC checks the payload size from the ‘Total size’ field of the PTD itself and
calculates the location of the next PTD header based on this information.
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
17 of 150
NXP [ NXP ]
