ISP1362
Single-chip USB OTG controller
Philips Semiconductors
9.4 PIO access to internal control registers
Table 5 shows the I/O port addressing in the ISP1362. The complete I/O port address
decoding should combine with the chip select signal (CS) and the address lines (A1
and A0). The direction of access of I/O ports, however, is controlled by the RD and
WR signals
When RD is LOW, the microprocessor reads data from the data port of the ISP1362
(see Figure 10). When WR is LOW, the microprocessor writes command to the
command port or writes data to the data port (see Figure 11).
Table 5:
I/O port addressing
CS
L
A1
A0
L
Access
Data bus width
16 bits
Description
L
R/W
W
HC data port
L
L
H
L
16 bits
HC command port
DC data port
L
H
H
R/W
W
16 bits
L
H
16 bits
DC command port
The register structure in the ISP1362 is a command-data register pair structure. A
complete register access needs a command phase followed by a data phase. The
command (also named as the index of a register) is used to inform the ISP1362 about
the register that will be accessed at the data phase.
On the 16-bit data bus of a microprocessor, a command occupies the lower byte and
the upper byte is filled with zeros (see Figure 12).
For 32-bit registers, the access cycle is shown in Figure 13. It consists of a command
phase followed by two data phases.
BUS INTERFACE
Host bus interface
0
µP bus interface
Device bus interface
1
A1
004aaa122
When A1 = L, microprocessor accesses the HC.
When A1 = H, microprocessor accesses the DC.
Fig 10. Microprocessor access to the HC or the DC.
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
21 of 150
NXP [ NXP ]
