ISP1362
Single-chip USB OTG controller
Philips Semiconductors
µP bus interface
[
]
[
]
D 15:0
D 15:0
RD
WR
CS
A1
RD
WR
CS
A2
MICRO-
PROCESSOR
ISP1362
A0
A1
INT1
INT2
IRQ1
IRQ2
004aaa042
Fig 8. PIO interface between a microprocessor and the ISP1362.
9.3 DMA mode
The ISP1362 also provides the DMA mode for external microprocessors to access
the internal buffer memory of the ISP1362. The DMA operation enables data to be
transferred between the system memory of a microprocessor and the internal buffer
memory of the ISP1362.
Remark: The DMA operation must be controlled by the DMA controller of the external
microprocessor system (master). Figure 9 shows the DMA interface between a
microprocessor system and the ISP1362.
The ISP1362 provides two DMA channels. The DMA channel 1 (controlled by the
DREQ1 and DACK1 signals) is for the DMA transfer between the system memory of
a microprocessor and the internal buffer memory of the ISP1362 HC. The DMA
channel 2 (controlled by the DREQ2 and DACK2 signals) is for the DMA transfer
between the system memory of a microprocessor and the internal buffer memory of
the ISP1362 DC. The ISP1362 provides an internal End-Of-Transfer (EOT) signal to
terminate the DMA transfer.
µP bus interface
[
]
[
]
D 15:0
D 15:0
RD
RD
WR
WR
MICRO-
PROCESSOR
DACK1
DREQ1
DACK1
DREQ1
ISP1362
DACK2
DREQ2
DACK2
DREQ2
004aaa043
Fig 9. DMA interface between a microprocessor and the ISP1362.
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
20 of 150
NXP [ NXP ]
