ISP1362
Single-chip USB OTG controller
Philips Semiconductors
16.2.4 Validate Endpoint Buffer (61H–6FH)
This command signals the presence of valid data for transmission to the USB host, by
setting the Buffer Full flag of the selected IN endpoint. This indicates that the data in
the buffer is valid and can be sent to the host, when the next IN token is received. For
a double-buffered endpoint, this command switches the current buffer memory for
CPU access.
Remark: For special aspects of the control IN endpoint, see Section 13.3.6.
Code (Hex): 61 to 6F — validate endpoint buffer (control IN, endpoint 1 to 14)
Transaction — none (code only)
16.2.5 Clear Endpoint Buffer (70H, 72H–7FH)
This command unlocks and clears the buffer of the selected OUT endpoint, allowing
the reception of new packets. Reception of a complete packet causes the Buffer Full
flag of an OUT endpoint to be set. Any subsequent packets are refused by returning a
NAK condition, until the buffer is unlocked using this command. For a double-buffered
endpoint, this command switches the current buffer memory for CPU access.
Remark: For special aspects of the control OUT endpoint, see Section 13.3.6.
Code (Hex): 70, 72 to 7F — clear endpoint buffer (control OUT, endpoint 1 to 14)
Transaction — none (code only)
16.2.6 DcEndpointStatusImage register (D0H–DFH)
This command is used to check the status of the selected endpoint buffer memory
without clearing any status or interrupt bits. The command accesses the
DcEndpointStatusImage register, which contains a copy of the DcEndpointStatus
register. The bit allocation of the DcEndpointStatusImage register is shown in
Table 126.
Code (Hex): D0 to DF — check status (control OUT, control IN, endpoint 1 to 14)
Transaction — write or read 1 byte (code or data)
Table 126: DcEndpointStatusImage register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
EPSTAL
EPFULL1
EPFULL0
DATA_PID
OVER
SETUPT
CPUBUF
reserved
WRITE
Reset
0
0
0
0
0
0
0
-
-
Access
R
R
R
R
R
R
R
Table 127: DcEndpointStatusImage register: bit description
Bit
Symbol
Description
7
EPSTAL
This bit indicates whether the endpoint is stalled or not
(1 = stalled; 0 = not stalled).
6
5
4
EPFULL1
EPFULL0
DATA_PID
Logic 1 indicates that the secondary endpoint buffer is full.
Logic 1 indicates that the primary endpoint buffer is full.
This bit indicates the data PID of the next packet
(0 = DATA0 PID; 1 = DATA1 PID).
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
122 of 150
NXP [ NXP ]
