Philips Semiconductors
Product specification
PowerMOS transistor
Avalanche energy rated
IRF840
PHP8N50
IF, Source-Drain diode current (Amps)
VGS = 0 V
20
15
10
5
PHP8N50E
Gate-source voltage, VGS (V)
15
14 ID = 8.5A
13
200V
Tj = 25 C
12
11
10
9
100V
8
VDD = 400 V
7
150 C
Tj = 25 C
6
5
4
3
2
1
0
0
20
40
Gate charge, QG (nC)
60
80
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
VSDS, Source-Drain voltage (Volts)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); parameter VDS
Fig.16. Source-Drain diode characteristic.
IF = f(VSDS); parameter Tj
Switching times (ns)
PHP8N50
1000
100
10
VDD = 250 V
VGS = 10 V
RD = 30 Ohms
Non-repetitive Avalanche current, IAS (A)
25 C
10
Tj = 25 C
Tj prior to avalanche = 125 C
td(off)
1
VDS
tp
tf
tr
ID
PHP8N50E
td(on)
0.1
1E-06
1E-05
1E-04
1E-03
1E-02
0
10
20
30
40
50
60
Avalanche time, tp (s)
RG, Gate resistance (Ohms)
Fig.14. Typical switching times; td(on), tr, td(off), tf = f(RG)
Fig.17. Maximum permissible non-repetitive
avalanche current (IAS) versus avalanche time (tp);
unclamped inductive load
Normalised Drain-source breakdown voltage
V(BR)DSS @ Tj
1.15
Maximum Repetitive Avalanche Current, IAR (A)
10
V(BR)DSS @ 25 C
1.1
Tj prior to avalanche = 25 C
1.05
1
125 C
1
0.1
0.95
0.9
PHP8N50E
1E-03 1E-02
0.01
1E-06
1E-05
1E-04
Avalanche time, tp (s)
0.85
-100
-50
0
50
100
150
Tj, Junction temperature (C)
Fig.15. Normalised drain-source breakdown voltage;
V(BR)DSS/V(BR)DSS 25 ˚C = f(Tj)
Fig.18. Maximum permissible repetitive avalanche
current (IAR) versus avalanche time (tp)
March 1999
5
Rev 1.000
NXP [ NXP ]
