NXP Semiconductors
HEF4094B
8-stage shift-and-store register
V
I
negative
pulse
0V
t
W
90 %
V
M
10 %
t
f
t
r
10 %
t
r
t
f
90 %
V
M
10 %
t
W
90 %
V
M
10 %
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90 %
V
M
V
I
positive
pulse
0V
a. Input waveform
V
EXT
V
DD
V
I
V
O
RL
G
RT
DUT
CL
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b. Test circuit
Test data is given in
Definitions for test circuit:
DUT = Device Under Test.
C
L
= load capacitance including jig and probe capacitance.
R
L
= load resistance.
R
T
= termination resistance should be equal to the output impedance Z
o
of the pulse generator.
Fig 11. Test circuit
Table 10.
V
DD
5 V to 15 V
Test data
Input
V
I
V
SS
or V
DD
t
r
, t
f
20 ns
V
EXT
t
PHL
, t
PLH
open
t
PHZ
, t
PZH
V
SS
t
PLZ
, t
PZL
V
DD
Load
C
L
50 pF
R
L
1 k
Supply voltage
HEF4094B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 11 — 29 August 2013
11 of 20
PHILIPS [ NXP SEMICONDUCTORS ]
