NXP Semiconductors
HEF4094B
8-stage shift-and-store register
Table 7.
Dynamic characteristics
…continued
V
SS
= 0 V; T
amb
= 25
C; for test circuit see
Figure 11;
unless otherwise specified.
Symbol
t
PLZ
Parameter
LOW to OFF-state
propagation delay
Conditions
OE to QPn;
see
V
DD
5V
10 V
15 V
t
su
set-up time
D to CP;
see
5V
10 V
15 V
t
h
hold time
D to CP;
see
5V
10 V
15 V
t
W
pulse width
minimum LOW 5 V
clock pulse;
10 V
see
15 V
minimum HIGH 5 V
strobe pulse;
10 V
see
15 V
f
max
maximum frequency
see
5V
10 V
15 V
[1]
Extrapolation formula
Min
-
-
-
60
20
15
+5
20
20
60
30
24
40
30
24
5
11
14
Typ
80
40
30
30
10
5
15
5
5
30
15
12
20
15
12
10
22
28
Max
160
80
60
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C
L
in pF).
Table 8.
Dynamic power dissipation
V
SS
= 0 V; t
r
= t
f
20 ns; T
amb
= 25
C.
Symbol
P
D
Parameter
dynamic power
dissipation
V
DD
5V
10 V
15 V
Typical formula for P
D
(W)
P
D
= 2100
f
i
+
(f
o
C
L
)
V
DD2
P
D
= 9700
f
i
+
(f
o
C
L
)
V
DD2
P
D
= 26000
f
i
+
(f
o
C
L
)
V
DD2
where:
f
i
= input frequency in MHz,
f
o
= output frequency in MHz,
C
L
= output load capacitance in pF,
V
DD
= supply voltage in V,
(f
o
C
L
) = sum of the outputs.
HEF4094B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 11 — 29 August 2013
8 of 20
PHILIPS [ NXP SEMICONDUCTORS ]
