HEF4017B-Q100
NXP Semiconductors
5-stage Johnson decade counter
CTRDIV10/DEC
3
&
2
1
14
13
15
0
CP1
13
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
3
CP0
2
14
4
CT = 0
2
3
4
5
6
7
8
9
4
7
7
10
1
10
1
5
5
6
15
MR
6
9
9
11
12
11
12
CT≥5
Q5-9
001aah239
001aah240
Fig 3. Logic symbol
Fig 4. IEE logic symbol
5. Pinning information
5.1 Pinning
+()ꢀꢁꢂꢃ%ꢄ4ꢂꢁꢁ
ꢁꢄ
ꢁꢀ
ꢁꢉ
ꢁꢈ
ꢁꢃ
ꢁꢁ
ꢁꢂ
ꢆ
ꢁ
ꢃ
ꢈ
ꢉ
ꢀ
ꢄ
ꢇ
ꢊ
4ꢀ
9
''
4ꢁ
4ꢂ
4ꢃ
4ꢄ
4ꢇ
4ꢈ
05
&3ꢂ
&3ꢁ
4ꢀꢅꢆ
4ꢆ
4ꢉ
9
66
4ꢊ
DDDꢀꢁꢂꢃꢁꢁꢄ
Fig 5. Pin configuration
HEF4017B_Q100
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© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 4 June 2014
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