74HC109-Q100; 74HCT109-Q100
NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge-trigger
W
:
9
,
ꢇꢄꢋꢍ
QHJDWLYHꢋ
SXOVH
9
9
9
9
0
0
0
ꢁꢄꢋꢍ
ꢇꢄꢋꢍ
*1'
W
W
U
I
W
W
I
U
9
,
SRVLWLYHꢋ
SXOVH
0
ꢁꢄꢋꢍ
*
*1'
W
:
9
&&
9
,
9
2
'87
5
7
&
/
ꢄꢄꢇDDKꢉꢂꢀꢊ
ꢊ
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
Fig 7. Test circuit for measuring switching times
Table 9.
Type
Test data
Input
VI
Load
Test
tr, tf
6 ns
6 ns
CL
74HC109-Q100
74HCT109-Q100
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
tPLH, tPHL
tPLH, tPHL
74HC_HCT109_Q100
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 28 September 2016
12 of 17
NXP [ NXP ]
