74HC109-Q100; 74HCT109-Q100
NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge-trigger
9
,
9
0
Q&3ꢋLQSXW
Q6'ꢋLQSXW
Q5'ꢋLQSXW
*1'
W
UHF
9
,
9
0
*1'
W
W
:
:
9
,
9
0
*1'
W
W
3/+
3+/
9
2+
9
9
Q4ꢋRXWSXW
Q4ꢋRXWSXW
0
9
2/
9
2+
0
9
2/
W
W
3/+
3+/
DDDꢃꢄꢅꢆꢄꢉꢄ
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Set and reset propagation delays, pulse widths and recovery time
Table 8.
Type
Measurement points
Input
VM
Output
VM
74HC109-Q100
74HCT109-Q100
0.5VCC
1.3 V
0.5VCC
1.3 V
74HC_HCT109_Q100
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 28 September 2016
11 of 17
NXP [ NXP ]
