PI6C2308
3.3V Zero Delay Buffer
SwitchingCharacteristicsforIndustrialTemperatureDevices(5)
Parameter
Name
Test Conditions
30pF load, All devices
Min. Typ. Max. Units
100
t1
Output Frequency
20pF load, 1H devices
10
134
134
MHz
15pF load, 1,2,3,4,6 devices
Measured at 1.4V, FOUT <66.66MHz 30pF load
Measured at 1.4V, FOUT <133 MHz 15pF load
Measured at 1.4V, FOUT <45 MHz 15pF load
Measured at 1.4V, FOUT <66.66MHz 30pF load
Measured at 1.4V, FOUT <133 MHz 15pF load
Measured at 1.4V, FOUT <45MHz 30pF load
Measured between 0.8V and 2.0V, 30pF load
Measured between 0.8V and 2.0V, 15pF load
Measured between 0.8V and 2.0V, 30pF load
Measured between 0.8V and 2.0V, 30pF load
Measured between 0.8V and 2.0V, 15pF load
Measured between 0.8V and 2.0V, 30pF load
Duty Cycle(4) = t2 ÷ t1
(1,2,3,4,6)
40.0
60.0
45.0
45.0
40.0
45.0
t2
50.0 55.0
%
Duty Cycle(4) = t2 ÷ t1 (1H)
60.0
55.0
2.2
Rise Time(4) (1,2,3,4)
Rise Time(4) (1H)
t3
1.50
1.50
2.50
1.50
1.25
ns
Fall Time(4) (1,2,3,4)
Fall Time(4) (1H)
t4
Output to Output Skew on same
Bank (1,2,3,4,6)(4)
200
400
Output Bank A to Output Bank B
Skew (1,1H, 4)
t5
All outputs equally loaded
Output Bank A to Output Bank B
Skew (2, 3,6)
ps
Delay, REF Rising Edge to FBK
Rising Edge(4)
t6
t7
t8
Measured at VDD/2
0
±200
600
Device to Device Skew(4)
Measured at VDD/2 MHz, on the FBK pins of devices
Measured twx 0.8V & 2.0V on 1H,5 device using Test
Crt #2
Output Slew Rate(4)
1
V/ns
ps
Cycle to Cycle Jitter(4),
(1, 1H, 4)
Measured at 66.67 MHz, loaded outputs, 30pF Load
Measured at 133 MHz, loaded outputs, 15pF Load
200
100
tJ
Cycle to Cycle Jitter(4),
(2,3,6)
Measured at 66.67 MHz, loaded outputs, 30pF Load
400
1.0
Stable power supply, valid clocks presented on REF &
FBK pins
tLOCK
PLL Lock Time(4)
ms
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
4. REF and FBK inputs have a threshhold voltage of V /2.
DD
5. For definition of t , see Switching Waveforms on page 8.
1-8
PS8384D
06/26/01
7
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
