PI6C2308
3.3V Zero Delay Buffer
Select Input Decoding for PI6C2308 (-1, -1H, -2, -3, -4)
S2
0
S1
0
CLKA [1-4]
Hi-Z
CLKB [1-4]
Hi-Z
Output Source
PLL Shutdown
PLL
PLL
Y
N
Y
N
0
1
Driven
Hi-Z
1
0
Driven
Driven
Driven
Reference
PLL
1
1
Driven
Select Input Decoding for PI6C2308-6
S2
0
S1
0
CLKA [1-4]
CLKB [1-4]
Hi-Z
Output Source
PLL
PLL Shutdown
Hi-Z
Y
Y
N
N
0
1
Driven = Reference
Driven = PLL
Driven = PLL
Driven = Reference/2
Driven = PLL
Driven = PLL/2
Reference
PLL
1
0
1
1
PLL
AvailablePI6C2308Configurations
Device
Feedback From
Bank A Frequency
Bank B Frequency
Reference
PI6C2308-1
PI6C2308-1H
PI6C2308-2
PI6C2308-2
PI6C2308-3
PI6C2308-3
PI6C2308-4
PI6C2308-6
PI6C2308-6
Bank A or Bank B
Bank A or Bank B
Bank A
Reference
Reference
Reference
Reference
Reference/2
Bank B
2X Reference
2X Reference
4X Reference
2X Reference
Reference
Reference
Bank A
Reference
Bank B
2X Reference
2X Reference
Reference or Reference/2
Reference
Bank A or Bank B
Bank A
Bank B
Reference or 2X Reference
PS8384D
06/26/01
2