PI6C2308
3.3V Zero Delay Buffer
SwitchingCharacteristics(5) forCommercialTemperatureDevice
Parameters
Name
Test Conditions
15pF to 30pF load
Min. Typ. Max. Units
t1
Output Frequency
10
45
134 MHz
55
Duty Cycle(5) = t2 ÷ t1 (2308-1H)
Measured at 1.4V, for high drive output
50
50
t2
%
Duty Cycle = t2 ÷ t1
(2308-1, -2, -3, -4, -6)
Measured at 1.4V, for normal drive output
40
60
Rise Time(4) @30pF
Rise Time(4) @15pF
Rise Time(4) @30pF (1H)
Fall Time(4) @30pF
2.2
1.5
t3
1.5
ns
Measured between 0.8V and 2.0V
2.2
t4
Fall Time(4) @15pF
1.5
Fall Time(4) @30pF (1H)
1.25
Output to Output Skew(4) on same
bank (23081,1H,2,3,4,6)
All outputs equally loaded, VDD/2
All outputs equally loaded, VDD/2
All outputs equally loaded, VDD/2
200
200
Output Bank A to Output Bank B
Skew(4) (23081,1H,4)
t5
Output Bank A to Output Bank B
Skew(4) (23082,3,6)
400
ps
t6
Input to Output Delay, REF Rising Edge
to FBK Rising Edge(4)
(Phase
Error)
Measured at VDD/2
0
0
±200
600
Measured at VDD/2 on the
FBK pins of devices
t7
t8
Device to Device Skew(4)
Output Slew Rate(4)
Measured between 0.8V and 2.0V on -
1H device using
1
V/ns
Test Circuit #2
Measured at 66.67 MHz,
loaded 30pF outputs
200
Cycle-to-Cycle Jitter(4)
(23081,1H,4)
tJ
tJ
Measured at 133 MHz,
loaded 15pF outputs
100
400
ps
Cycle-to-Cycle Jitter(4)
(23082,3,6)
Measured at 66.6 MHz,
loaded 30pF outputs
Stable power supply, valid clocks
presented on REF and FBK pins
tLOCK
PLL Lock Time(4)
1.0
ms
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
4. REF and FBK inputs have a threshhold voltage of V /2.
DD
5. For definition of t , see Switching Waveforms on page 8.
1-8
PS8384D
06/26/01
5
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
