PE3342
Product Specification
Table 6. AC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Max
Units
Control Interface and Registers (see Figure 4)
fClk
tClkH
tClkL
tDSU
tDHLD
tPW
Serial data clock frequency
(Note 1)
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Serial clock HIGH time
30
30
10
10
30
30
30
30
30
Serial clock LOW time
Data set-up time to Clock rising edge
Data hold time after Clock rising edge
S_WR pulse width
tCWR
tCE
tWRC
tEC
Clock rising edge to S_WR rising edge
Clock falling edge to E_WR transition
S_WR falling edge to Clock rising edge
E_WR transition to Clock rising edge
EEPROM Erase/Write Programming (see Figures 5 & 6)
tEESU
ns
ms
µs
EELoad rising edge to VPP rising edge
500
25
1
tEEPW
VPP pulse width
30
tVPP
VPP pulse rise and fall times
(Note 2)
Main Divider (Including Prescaler)
FIn
FIn
Operating frequency
Operating frequency
Input level range
300
300
-5
2700
3000
5
MHz
MHz
dBm
Speed-grade option (Note 3)
External AC coupling
PFIn
Main Divider (Prescaler Bypassed)
FIn
Operating frequency
Input level range
(Note 4)
50
-5
270
5
MHz
dBm
PFIn
External AC coupling (Note 4)
Reference Divider
fr
Operating frequency
(Note 5)
100
20
MHz
dBm
Pfr
Reference input power (Note 4)
Single ended input
-2
Phase Detector
fc
Comparison frequency
(Note 6)
MHz
SSB Phase Noise (Fin = 1.3 GHz, fr = 10 MHz, fc = 1.25 MHz, LBW = 70 kHz, VDD = 3.0 V, Temp = -40° C)
100 Hz Offset
1 kHz Offset
-75
-85
dBc/Hz
dBc/Hz
Note 1: fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fClk
specification.
Note 2: Rise and fall times of the VPP programming voltage pulse must be greater than 1 µs.
Note 3: The maximum frequency of operation can be extended to 3.0 GHz by ordering a special speed-grade option. Please refer to Table 14,
Ordering Information, for ordering details.
Note 4: CMOS logic levels can be used to drive FIn input if DC coupled and used in Prescaler Bypass mode. Voltage input needs to be a minimum
of 0.5 Vp-p. For optimum phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns. No minimum
frequency limit exists when operated in this mode.
Note 5: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum
phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns.
Note 6: Parameter is guaranteed through characterization only and is not tested.
Document No. 70-0091-03 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
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