PE3342
Product Specification
Figure 2. Pin Configurations (Top View)
Figure 3. Package Types
24-lead TSSOP, 20-lead QFN
1
2
24
23
22
21
20
19
18
17
16
15
14
13
VDD
GND
ENH
S_WR
Data
Clock
GND
FSel
E_WR
VPP
fr
GND
EESel
PD_U
PD_D
VDD
3
4
5
1
2
3
4
5
15
14
13
12
11
S_WR
Data
PD_D
VDD
6
24-lead TSSOP
20-lead QFN
4x4mm
7
Dout
LD
Clock
FSel
Dout
LD
Exposed Solder Pad
(Bottom Side)
8
9
E_WR
EELoad
EELoad
Cext
GND
Fin
10
11
12
VDD
Fin
Table 2. Pin Descriptions
Pin No.
TSSOP
Pin No.
QFN
Pin Name
Type
Description
19
VDD
(Note 1)
(Note 2)
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required.
Ground.
1
2
GND
Enhancement mode control line. When asserted LOW, enhancement register bits are
functional. Internal 70 kΩ pull-up resistor.
20
ENH
Input
3
Secondary Register WRITE input. Primary Register contents are copied to the
Secondary Register on S_WR rising edge. Also used to control Serial Port operation
and EEPROM programming.
4
1
2
3
S_WR
Data
Input
Input
Input
Binary serial data input. Input data entered LSB (B0) first.
5
6
Serial clock input. Data is clocked serially into the 20-bit Primary Register, the 20-bit
EE Register, or the 8-bit Enhancement Register on the rising edge of Clock. Also used
to clock EE Register data out Dout port.
Clock
GND
FSel
(Note 2)
Input
Ground.
7
8
4
5
Frequency Register selection control line. Internal 70 kΩ pull-down resistor.
Enhancement Register write enable. Also functions as a Serial Port control line.
Internal 70 kΩ pull-down resistor.
E_WR
VPP
Input
Input
9
EEPROM erase/write programming voltage supply pin. Requires a 100pF bypass
capacitor connected to GND.
6
10
7
8
VDD
Fin
(Note 1)
Input
Same as pin 1.
11
12
Prescaler input from the VCO.
Prescaler complementary input. A series 50 Ω resistor and DC blocking capacitor
9
Fin
Input
13
14
should be placed as close as possible to this pin and connected to the ground plane.
GND
(Note 2)
Ground.
Logical “NAND” of PD_U and PD_D terminated through an on-chip, 2 kΩ series
resistor. Connecting CEXT to an external capacitor will low pass filter the input to the
inverting amplifier used for driving LD.
10
CEXT
Output
15
Control line for Serial Data Port, Frequency Register selection, EE Register parallel
loading, and EEPROM programming. Internal 70 kΩ pull-down resistor.
11
12
EELoad
LD
Input
16
17
Lock detect output, an open-drain logical inversion of CEXT. When the loop is in lock,
LD is high impedance; otherwise, LD is a logic LOW.
Output, OD
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0091-03 │ UltraCMOS™ RFIC Solutions
Page 2 of 17
PSEMI [ Peregrine Semiconductor ]
