PE3342
Product Specification
Pin No.
TSSOP
Pin No.
QFN
Pin Name
Type
Description
Data out function. Dout is defined with the Enhancement Register and enabled with
13
Dout
VDD
Output
18
19
20
21
22
ENH.
Same as pin 1.
14
15
(Note 1)
Output
PD_D
Phase detector output. PD_D pulses negatively when fp leads fc.
PD_U
16
17
Output
Input
Phase detector output. PD_U pulses negatively when fc leads fp.
Control line for Frequency Register selection, EE Register parallel loading, and
EEPROM programming. Internal 70 kΩ pull-up resistor.
EESel
GND
fr
(Note 2)
Input
Ground.
23
24
18
Reference frequency input.
Notes 1: VDD pins 1, 11, and 19 (TSSOP) or pins 6, 14 and 19 (QFN), are connected by diodes and must be supplied with the same positive voltage
level.
2: Ground connections are made through the exposed solder pad. The solder pad must be soldered to the ground plane for proper operation .
Table 2. Absolute Maximum Ratings
Table 4. ESD Ratings
Symbol Parameter/Conditions Min
Max
Units
Symbol Parameter/Conditions
Min
Max
Units
VDD
VI
Supply voltage
–0.3
–0.3
+4.0
V
V
VESD
ESD voltage human body
model (Note 1)
1000
V
Voltage on any digital
input
Storage temperature
range
VDD+0.3
VESD
ESD voltage human body
model (Note 1)
200
V
(VPP
)
TStg
–65
+85
°C
Note 1: Periodically sampled, not 100% tested. Tested per MIL-
STD-883, M3015 C2
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the DC and AC Characteristics table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating in Table 4.
Table 3. DC Electrical Specifications
Latch-Up Avoidance
Symbol Parameter/Conditions
Min
2.85
-40
Max
3.15
85
Units
V
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
VDD
TA
Supply voltage
Operating ambient
temperature range
°C
Document No. 70-0091-03 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
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