PE3342
Product Specification
Lock Detect Output
Serial Data Port
A lock detect signal is provided at pin LD, via the
pin CEXT (see Figure 1). CEXT is the logical “NAND”
of PD_U and PD_D waveforms, driven through a
series 2k ohm resistor. When the loop is locked,
this output will be HIGH with narrow pulses LOW.
Connecting CEXT to an external shunt capacitor
provides integration of this signal.
The Serial Data Port allows control data to be
entered into the device. This data can be directed
into one of three registers: the Enhancement
register, the Primary register, and the EE register.
Table 7 defines the control line settings required
to select one of these destinations.
Input data presented on pin 5 (Data) is clocked
serially into the designated register on the rising
edge of Clock. Data is always loaded LSB (B0)
first into the receiving register. Figure 4 defines
the timing requirements for this process .
The CEXT signal is sent to the LD pin through an
internal inverting comparator with an open drain
output. Thus LD is an “AND” function of PD_U
and PD_D.
Table 7. Serial Interface
S_WR
E_WR
EELoad
Register Loaded
0
0
0
0
1
0
0
1
Primary Register
Enhancement Register
EE Register
X
Figure 4. Serial Interface Timing Diagram
Data
E_WR
EELoad
tEC
tCE
Clock
S_WR
tDSU
tDHLD
tClkH
tClkL
tCWR
tPW
tWRC
Document No. 70-0091-03 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
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