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OXCB950-TQAG 参数 Datasheet PDF下载

OXCB950-TQAG图片预览
型号: OXCB950-TQAG
PDF下载: 下载PDF文件 查看货源
内容描述: 集成的高性能UART的Cardbus / 3.3V PCI接口 [Integrated High Performance UART Cardbus / 3.3v PCI interface]
分类和应用: PC
文件页数/大小: 67 页 / 598 K
品牌: OXFORD [ OXFORD SEMICONDUCTOR ]
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OXCB950  
OXFORD SEMICONDUCTOR LTD.  
6.2 Configuration space  
The device dependant region of the PCI configuration  
space contains the cardbus/pci Power Management  
Extended Capability register set and (for the cardbus mode  
only) the Tuples making up the Cardbus Information  
Structure.  
The OXCB950 is a single function device, with one PCI  
configuration space (and for the default cardbus mode, one  
cardbus information structure).  
The format of the PCI configuration space, for cardbus and  
pci modes, is as shown in the Table below.  
All the required fields in the predefined PCI header region  
have been implemented. This includes those fields in the  
cardbus PC Card Standard that are termed “allocated” and  
“reserved” for cardbus applications. This implementation is  
a specific requirement for cardbus support in Windows 9x.  
In general, writes to any registers that are not implemented  
are ignored, and all reads from unimplemented registers  
return 0.  
6.2.1 Cardbus / PCI Configuration Space Register map  
Configuration Register Description  
Offset  
Address  
00h  
31  
16  
15  
0
Device ID  
Status  
Vendor ID  
Command  
04h  
Class Code  
Header Type  
Revision ID  
Reserved  
08h  
1
BIST  
Reserved  
0Ch  
Base Address Register 0 (BAR0) – UART Function in I/O space  
Base Address Register 1 (BAR 1) - UART Function in Memory space  
10h  
14h  
Base Address Register 2 (BAR 2) – Local Configuration Registers in IO space  
Base Address Register 3 (BAR3) – Local Configuration Registers in Memory space  
Base Address Register 4 (BAR4) – Cardbus Status Registers in Memory Space  
Function Event : Offset +0  
18h  
1Ch  
20h  
Function Event Mask : Offset +4  
Function Present State : Offset +8  
Function Force Event : Offset +12  
Reserved (Bar 5)  
24h  
28h  
2Ch  
30h  
34h  
38h  
3Ch  
Cardbus CIS Pointer  
Subsystem ID  
Subsystem Vendor ID  
Cap_Ptr  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Interrupt Pin  
Interrupt Line  
Predefined PCI Header Region  
Device Dependent PCI Region  
Power Management Capabilities (PMC)  
Next Ptr  
Cap_ID  
40h  
44h  
48h  
4Ch  
Reserved  
Reserved  
PMC Control/Status Register (PMCSR)  
Tuple Byte3*  
Tuple Byte 2*  
Tuple Byte1*  
Tuple Byte 0*  
Tuple Byte n*  
Tuple Byte (n+1)*  
* Tuples are available for the Cardbus mode only. These fields return all 0’s for the PCI mode of the device.  
Table 2: Cardbus/PCI Configuration space  
DS-0033 Sep 05  
External-Free Release  
Page 14  
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