OX16C950 rev B
OXFORD SEMICONDUCTOR LTD.
14 BAUD RATE GENERATION
DLM:DLL
Divisor Word
0x0900
0x0300
0x0180
0x00C0
0x0060
0x0030
0x0018
0x000C
0x0006
0x0004
0x0003
0x0002
0x0001
Baud Rate
(bits per second)
14.1
General Operation
The UART contains a programmable baud rate generator
that is capable of taking any clock input from DC to 60MHz
(at 5V) and dividing it by any 16-bit divisor number from 1
to 65535 written into the DLM (MSB) and DLL (LSB)
registers. In addition to this, a clock prescaler register is
provided which can further divide the clock by values in the
range 1.0 to 31.875 in steps of 0.125. Also, a further
feature is the Times Clock Register ‘TCR’ which allows the
sampling clock to be set to any value between 4 and 16.
50
110
300
600
1,200
2,400
4,800
9,600
19,200
28,800
38,400
57,600
115,200
These clock options allow for highly flexible baud rate
generation capabilities from almost any input clock
frequency (up to 60MHz). The actual transmitter and
receiver baud rate is calculated as follows:
InputClock
SC * Divisor * prescaler
BaudRate =
Table 15: Standard PC COM Port Baud Rate Divisors
(assuming a 1.8432MHz crystal)
Where:
SC
= Sample clock values defined in TCR[3:0]
Divisor = DLL + ( 256 x DLM )
Prescaler = 1 when MCR[7] = ‘0’ else:
= M + ( N / 8 ) where:
M
N
= CPR[7:3] (Integer part – 1 to 31)
= CPR[2:0] (Fractional part – 0.000 to 0.875 )
See next section for a discussion of the clock prescaler and
times clock register.
After a hardware reset, the prescaler is bypassed (set to 1)
and TCR is set to 0x00 (i.e. SC = 16). Assuming this
default configuration, the following table gives the divisors
required to be programmed into the DLL and DLM registers
in order to obtain various standard baud rates:
Data Sheet Revision 1.2
Page 30
OXFORD [ OXFORD SEMICONDUCTOR ]
