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OX16C950-PCC60-B 参数 Datasheet PDF下载

OX16C950-PCC60-B图片预览
型号: OX16C950-PCC60-B
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能UART与128字节的FIFO [High Performance UART with 128 byte FIFOs]
分类和应用: 先进先出芯片
文件页数/大小: 49 页 / 436 K
品牌: OXFORD [ OXFORD SEMICONDUCTOR ]
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OX16C950 rev B  
OXFORD SEMICONDUCTOR LTD.  
13 AUTOMATIC FLOW CONTROL  
Automatic in-band flow control, automatic out-of-band flow  
control and special character detection features can be  
used when in Enhanced mode and are software compatible  
with the 16C654. Alternatively, 16C750 compatible  
automatic out-of-band flow control can be enabled when in  
non-Enhanced mode. In 950 mode, in-band and out-of-  
band flow controls are compatible with 16C654, with the  
addition of fully programmable flow control thresholds.  
EFR[3:2]: In-band transmit flow control mode  
When in-band transmit flow control is enabled, an  
XON/XOFF character is inserted into the data stream  
whenever the RFL passes the upper trigger level and falls  
below the lower trigger level respectively.  
For automatic in-band flow control, bit 4 of EFR must be  
set. The combinations of software transmit flow control can  
then be selected by programming EFR[3:2] as follows:  
13.1 Enhanced Features Register ‘EFR’  
logic [00] In-band transmit flow control is disabled.  
logic [01] Single character in-band transmit flow  
control enabled, using XON2 as the XON  
character and XOFF2 as the XOFF  
character.  
logic [10] Single character in-band transmit flow  
control enabled, using XON1 as the XON  
character and XOFF1 as the XOFF  
character.  
Writing 0xBF to LCR enables access to the EFR and other  
Enhanced mode registers. This value corresponds to an  
unused data format. Writing 0xBF to LCR will set LCR[7]  
but leaves LCR[6:0] unchanged. Therefore, the data format  
of the transmitter and receiver data is not affected. Write  
the desired LCR value to exit from this selection.  
Note: In-band transmit and receive flow control is disabled  
in 9-bit mode.  
Logic[11] The value EFR[3:2] = “11” is reserved for  
future use and should not be used  
EFR[1:0]: In-band receive flow control mode  
When in-band receive flow control is enabled, the UART  
compares the received data with the programmed XOFF  
character. When this occurs, the UART will disable  
transmission as soon as any current character  
transmission is complete. The UART then compares the  
received data with the programmed XON character. When  
a match occurs, the UART will re-enable transmission (see  
section 15.6).  
EFR[4]: Enhanced mode  
logic 0 Non-Enhanced mode. Disables IER bits 4-7,  
ISR bits 4-5, FCR bits 4-5, MCR bits 5-7 and  
in-band flow control. Whenever this bit is  
cleared, the setting of other bits of EFR are  
ignored.  
logic 1 Enhanced mode. Enables the Enhanced Mode  
functions. These functions include enabling  
IER bits 4-7, FCR bits 4-5, MCR bits 5-7. For  
in-band flow control the software driver must  
set this bit first. If this bit is set, out-of-band  
flow control is configured with EFR bits 6-7,  
otherwise out-of-band flow control is  
compatible with 16C750.  
For automatic in-band flow control, bit 4 of EFR must be  
set. The combinations of software receive flow control can  
be selected by programming EFR[1:0] as follows:  
logic [00] In-band receive flow control is disabled.  
logic [01] Single character in-band receive flow control  
enabled, recognising XON2 as the XON  
character and XOFF2 as the XOFF  
character.  
logic [10] Single character in-band receive flow control  
enabled, recognising XON1 as the XON  
character and XOFF1 and the XOFF  
character.  
logic [11] The behavior of the receive flow control is  
dependent on the configuration of EFR[3:2].  
single character in-band receive flow control  
is enabled, accepting both XON1 and XON2  
as valid XON characters and both XOFF1  
and XOFF2 as valid XOFF characters when  
EFR[3:2] = “01” or “10”. EFR[1:0] should not  
be set to “11” when EFR[3:2] is either “00”.  
EFR[5]: Enable special character detection  
logic 0 Special character detection is disabled.  
logic 1 While in Enhanced mode (EFR[4]=1), the  
UART compares the incoming receiver data  
with the XOFF2 value. Upon a correct match,  
the received data will be transferred to the  
RHR and a level 5 interrupt (XOFF or special  
character) will be asserted if level 5 interrupts  
are enabled (IER[5] set to 1).  
Data Sheet Revision 1.2  
Page 28  
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