OX16C950 rev B
OXFORD SEMICONDUCTOR LTD.
In this mode, the receiver and transmitter interrupts are
fully operational. The modem control interrupts are also
operational, but the interrupt sources are now the lower
four bits of the Modem Control Register instead of the four
modem status inputs. The interrupts are still controlled by
the IER.
11.2 Modem Status Register ‘MSR’
MSR[0]: Delta CTS#
Indicates that the CTS# input has changed since the last
time the MSR was read.
MSR[1]: Delta DSR#
Indicates that the DSR# input has changed since the last
time the MSR was read.
MCR[5]: Enable XON-Any in Enhanced mode or enable
out-of-band flow control in non-Enhanced mode
650/950 modes (Enhanced mode):
logic 0 ⇒ XON-Any is disabled.
logic 1 ⇒ XON-Any is enabled.
MSR[2]: Trailing edge RI#
Indicates that the RI# input has changed from low to high
since the last time the MSR was read.
In enhanced mode (EFR[4]=1), this bit enables the Xon-
Any operation. When Xon-Any is enabled, any received
data will be accepted as a valid XON (see in-band flow
control, section 13.3).
MSR[3]: Delta DCD#
Indicates that the DCD# input has changed since the last
time the MSR was read.
MSR[4]: CTS
750 mode (Non-Enhanced mode):
logic 0 ⇒ CTS/RTS flow control disabled.
logic 1 ⇒ CTS/RTS flow control enabled.
This bit is the complement of the CTS# input. It is
equivalent to RTS (MCR[1]) during internal loop-back
mode.
In non-enhanced mode, this bit enables the CTS/RTS out-
of-band flow control.
MSR[5]: DSR
This bit is the complement of the DSR# input. It is
equivalent to DTR (MCR[0]) during internal loop-back
mode.
MCR[6]: IrDA mode
logic 0 ⇒ Standard serial receiver and transmitter data
format.
MSR[6]: RI
This bit is the complement of the RI# input. In internal loop-
back mode it is equivalent to the internal OUT1.
logic 1 ⇒ Data will be transmitted and received in IrDA
format.
MSR[7]: DCD
This function is only available in Enhanced mode. It
requires a 16x clock to function correctly.
This bit is the complement of the DCD# input. In internal
loop-back mode it is equivalent to the internal OUT2.
MCR[7]: Baud rate prescaler select
logic 0 ⇒ Normal (divide by 1) baud rate generator
prescaler selected.
logic 1 ⇒ Divide-by-“M N/8” baud rate generator
prescaler selected.
Where M & N are programmed in CPR (ICR offset 0x01).
After a hardware reset, CPR defaults to 0x20 (divide-by-4)
and MCR[7] is loaded with the complement of the CLKSEL
pin. User writes to this flag will only take effect in enhanced
mode. See section 13.1.
Data Sheet Revision 1.2
Page 26
OXFORD [ OXFORD SEMICONDUCTOR ]
