OX16C950 rev B
OXFORD SEMICONDUCTOR LTD.
MODE SELECTION
5
The OX16C950 device is a single channel device software compatible with the 16C450, 16C550, 16C654 and 16C750 UARTs.
The operation of the OX16C950 depends on a number of mode settings. These modes are referred to throughout this data
sheet. The FIFO depth and compatibility modes are tabulated below:
UART Mode
FIFO
size
1
FCR[0]
Enhanced mode
(EFR[4]=1)
X
FCR[5]
(guarded with LCR[7] = 1)
FIFOSEL
pin
X
450
0
X
550
Extended 550
650
16
1
1
1
1
1
0
0
1
0
1
0
X
X
1
0
1
X
0
X
128
128
128
128
750
950*
X
Table 3: UART Mode Configuration
* Note that 950 mode configuration is identical to 650 configuration
guard. Once FCR[5] is set, the software should clear
LCR[7] for normal operation.
5.1
450 Mode
After a hardware reset bit 0 of the FIFO Control Register
(‘FCR’) is cleared, hence OX16C950 is compatible with the
16C450. The transmitter and receiver FIFOs (referred to as
the ‘Transmit Holding Register’ and ‘Receiver Holding
Register’ respectively) have a depth of one. This is referred
to as ‘Byte mode’. When FCR[0] is cleared, all other mode
selection parameters are ignored.
The 16C750 additional features over the 16C550 are
available as long as the UART is not put into Enhanced
mode (i.e. EFR[4] should be ‘0’). These features are:
1. Deeper FIFOs
2. Automatic RTS/CTS out-of-band flow control
3. Sleep mode
5.2
550 Mode
5.5
650 Mode
Connect FIFOSEL to GND or leave it unconnected. After a
hardware reset, writing a 1 to FCR[0] will increase the FIFO
size to 16, providing compatibility with 16C550 devices.
Since this pin is a no-connect in 16C550 devices, replacing
a 16C550 with OX16C950 would result in a 550 compatible
device with 16 byte deep FIFOs.
The OX16C950 is compatible with the 16C650 when
EFR[4] is set, i.e. the device is in Enhanced mode. As 650
software drivers usually put the device into Enhanced
mode, running 650 drivers on the OX16C950 device will
result in 650 compatibility with 128 deep FIFOs, as long as
FCR[0] is set. This is regardless of the state of the
FIFOSEL pin or package option. Note that the 650
emulation mode of the OX16C950 provides 128 byte deep
FIFOs whereas the standard 16C650 has only 32 byte
FIFOs.
5.3
Extended 550 Mode
Connect FIFOSEL to VDD. Writing a 1 to FCR[0] will now
increase the FIFO size to 128, thus providing a 550 device
with 128 deep FIFOs.
650 mode has the same enhancements as the 16C750
over the 16C550, but these are enabled using different
registers.
5.4
750 Mode
For compatibility with 16C750, leave FIFOSEL
unconnected.
There are also additional enhancements over those of the
16C750 in this mode, these are:
Writing a 1 to FCR[0] will increase the FIFO size to 16. In a
similar fashion to 16C750, the FIFO size can be further
increased to 128 by writing a 1 to FCR[5]. Note that access
to FCR[5] is protected by LCR[7]. I.e., to set FCR[5],
software should first set LCR[7] to temporarily remove the
1. Automatic in-band flow control
2. Special character detection
3. Infra-red “IrDA-format” transmit and receive mode
4. Transmit trigger levels
5. Optional clock prescaler
Data Sheet Revision 1.2
Page 13
OXFORD [ OXFORD SEMICONDUCTOR ]
