OX16C950 rev B
OXFORD SEMICONDUCTOR LTD.
REGISTER DESCRIPTION TABLES
6
The three address lines select the various registers in the UART. Since there are more than 8 registers, selection of the registers
is also dependent on the state of the Line Control Register ‘LCR’ and Additional Control Register ‘ACR’:
1. LCR[7]=1 enables the divider latch registers DLL and DLM.
2. LCR specifies the data format used for both transmitter and receiver. Writing 0xBF (an unused format) to LCR enables
access to the 650 compatible register set. Writing this value will set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the
data format of the transmitter and receiver data is not affected. Write the desired LCR value to exit from this selection.
3. ACR[7]=1 enables access to the 950 specific registers.
4. ACR[6]=1 enables access to the Indexed Control Register set (ICR) registers as described on page 17.
Register Address R/W
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
THR
000
W
Data to be transmitted
Data received
1
RHR
000
R
1,2
IER
CTS
interrupt
mask
RTS
interrupt
mask
Special
Char.
Detect
650/950
Mode
Modem
Sleep
Rx Stat
interrupt interrupt
mask
THRE
RxRDY
interrupt
mask
001
010
R/W
W
interrupt
mode
Alternate
sleep
mode
THR Trigger
Level
FIFO
Size
mask
mask
550/750
Mode
Unused
3
FCR
RHR Trigger
Level
RHR Trigger
Level
DMA
Mode /
Tx
Trigger
Enable
650 mode
Flush
THR
Flush
RHR
Enable
FIFO
750 mode
Unused
950 mode
Unused
FIFOs
enabled
Interrupt priority
(Enhanced mode)
Interrupt priority
(All modes)
Interrupt
pending
3
ISR
010
011
R
Divisor
Odd /
Number
of stop
bits
Tx
break
Force
even
Parity
enable
4
LCR
R/W
latch
Data length
parity
parity
access
CTS &
RTS
Flow
3,4
MCR
Internal
Loop
Back
550/750
Mode
Unused
OUT2
(Int En)
100
R/W
OUT1
RTS
DTR
Control
Enable
650/950
Mode
Baud
prescale
IrDA
mode
XON-Any
3,5
LSR
Data
Error
THR
Empty
Rx
Break
Framing
Error
Parity
Error
9th Rx
data bit
Trailing
RI edge
Overrun
Error
Tx Empty
RxRDY
Normal
101
110
111
R
R
9-bit data
mode
Delta
DCD
Delta
DSR
Delta
CTS
3
MSR
DCD
RI
DSR
CTS
3
SPR
Temporary data storage register and
Indexed control register offset value bits
Normal
R/W
9-bit data
mode
9th Tx
data bit
Unused
Additional Standard Registers – These registers require divisor latch access bit (LCR[7]) to be set to 1.
DLL
000
R/W
Divisor latch bits [7:0] (Least significant byte)
DLM
001
R/W
Divisor latch bits [15:8] (Most significant byte)
Table 4: Standard 550 Compatible Registers
Data Sheet Revision 1.2
Page 15
OXFORD [ OXFORD SEMICONDUCTOR ]
