OX16C950 rev B
OXFORD SEMICONDUCTOR LTD.
5.6
950 Mode
The UART has a flexible prescaler capable of dividing the
system clock by any value between 1 and 31.875 in steps
of 0.125. It divides the system clock by an arbitrary value in
“M N/8” format, where M and N are 5 and 3-bit binary
numbers programmed in CPR[7:3] and CPR[2:0]
respectively. This arrangement offers a great deal of
flexibility when choosing an input clock frequency to
synthesize arbitrary baud rates. The default division value
is 4 to provide backward compatibility with 16C650
devices.
The additional features offered in OX16C950 (950 mode)
generally only apply when the UART is in Enhanced mode
(EFR[4]=’1’). Provided FCR[0] is set, in Enhanced mode
the FIFO size is 128 regardless of the state of FIFOSEL.
Note that 950 mode configuration is identical to that of 650
mode, however additional 950 specific features are
enabled using the Additional Control Register ‘ACR’ (see
section 15.3). In addition to larger FIFOs and higher baud
rates, the enhancements of the 16C950 over the 16C654
are:
The user may apply an external 1x (or Nx) clock for the
transmitter and receiver to the RI# and DSR# pin
respectively. The transmitter clock may be asserted on the
DTR# pin. The external clock options are selected through
the CKS register (offset 0x02 of ICR).
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Selectable arbitrary trigger levels for the receiver and
transmitter FIFO interrupts
Improved automatic flow control using selectable
arbitrary thresholds
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DSR#/DTR# automatic flow control
Transmitter and receiver can be optionally disabled
Software reset of device
It is also possible to define the over-sampling rate used by
the transmitter and receiver clocks. The 16C450/16C550
and compatible devices employ 16 times over-sampling,
i.e. There are 16 clock cycles per bit. However, OX16C950
can employ any over-sampling rate from 4 to 16 by
programming the TCR register. This allows the data rates
to be increased to 460.8 Kbps using a 1.8432MHz clock, or
15 Mbps using a 60 MHz clock. The default value after a
reset for this register is 0x00, which corresponds to a 16
cycle sampling clock. Writing 0x01, 0x02 or 0x03 will also
result in a 16 cycle sampling clock. To program the value to
any value from 4 to 15 it is necessary to write this value
into TCR i.e. to set the device to a 13 cycle sampling clock
it would be necessary to write 0x0D to TCR. For further
information see sections 14.3.
Readable FIFO fill levels
Optional generation of an RS-485 buffer enable signal
Four-byte device identification (0x16C95003)
Readable status for automatic in-band and out-of-
band flow control
External 1x clock modes (see section 14.4)
Flexible “M N/8” clock prescaler (see section 14.2)
Programmable sample clock to allow data rates up to
15 Mbps (see section 14.3)
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9-bit data mode
The 950 trigger levels are enabled when ACR[5] is set (bits
4 to 7 of FCR are ignored). Then arbitrary trigger levels can
be defined in RTL, TTL, FCL and FCH registers (see
section 15). The Additional Status Register (‘ASR’) offers
flow control status for the local and remote transmitters.
FIFO levels are readable using RFL and TFL registers.
The OX16C950 also offers 9-bit data frames for multi-drop
industrial applications.
Data Sheet Revision 1.2
Page 14
OXFORD [ OXFORD SEMICONDUCTOR ]
