NCN8024R
PIN FUNCTION AND DESCRIPTION
Pin #
Name
Type
Description
11
CRD_I/O
Input/
This pin handles the connection to the serial I/O (C7) of the card connector. A bi−directional level
Output translator adapts the serial I/O signal between the card and the micro controller. An 11 kW (typical)
pullup resistor to CRD_V provides a High impedance state for the smart card I/O link.
CC
12
13
CRD_AUX2
CRD_AUX1
Input/
This pin handles the connection to the chip card’s serial auxiliary AUX2 I/O pin (C8). A bi−directional
Output level translator adapts the serial I/O signal between the card and the micro controller. An 11 kW
(typical) pullup resistor to CRD_V provides a High impedance state for the smart card C8 pin.
CC
Input/
This pin handles the connection to the chip card’s serial auxiliary AUX1 I/O pin (C4). A bi−directional
Output level translator adapts the serial I/O signal between the card and the micro controller. An 11 kW
(typical) pullup resistor to CRD_V provides a High impedance state for the smart card C4 pin.
CC
14
15
CRD_GND
CRD_CLK
GND
Card Ground
Output This pin is connected to the CLOCK card connector’s pin (Chip card’s pin C3). The Clock signal
comes from the CLKIN input through clock dividers and level shifter.
16
17
CRD_RST
CRD_VCC
Output This pin is connected to the chip card’s RESET pin (C2) through the card connector. A level
translator adapts the external Reset (RSTIN) signal to the smart card.
Power This pin is connected to the smart card power supply pin. An internal DC/DC converter is
programmable using the pin 5V/3V to supply either 5 V or 3 V output voltage. An external distributed
ceramic capacitor ranging from 80 nF to 1.2 mF recommended must be connected across
CRD_VCC and CRD_GND. This set of capacitor must be low ESR (< 100 mW).
18
19
20
PORADJ
CMDVCC
RSTIN
Input
Input
Input
Power−on reset threshold adjustment input pin for changing the reset threshold with an external
resistor power divider. Recommended to be connected to ground when unused.
Command VCC pin. Activation sequence Enable/Disable pin (active Low). The activation sequence is
enabled by toggling CMDVCC High to Low and when a card is present.
This Reset input connected to the host and referred to V (microcontroller side), is connected to
DD
the smart card Reset pin through the internal level shifter which translates the level according to the
CRD_V programmed value.
CC
21
VDD
Power This pin is connected to the system controller power supply. It configures the level shifter input
stage to accept the signals coming from the controller. A 0.1 mF capacitor shall be used to bypass
the power supply voltage. When V is below 2.30 V typical the card pins are disabled.
DD
22
23
GND
INT
GND
Ground
Output The interrupt request is activated LOW on this pin. This is enabled when a card is present and the
card presence is detected by CRD_PRES or CRD_PRES pins. Similarly an interrupt is generated
when CRD_V is overloaded. 20 kW typical integrated pullup resistor to V
.
CC
DD
24
25
26
CLKIN
NC
Input
Clock Input for External Clock
Not Connected
I/Ouc
Input/
This pin is connected to an external micro−controller. A bi−directional level translator adapts the
Output serial I/O signal between the smart card and the external controller. A built−in constant 11 kW
(typical) resistor provides a high impedance state.
27
28
AUX1uc
AUX2uc
Input/
This pin is connected to an external micro−controller. A bi−directional level translator adapts the
Output serial C4 signal between the smart card and the external controller. A built−in constant 11 kW
(typical) resistor provides a high impedance state.
Input/
This pin is connected to an external micro−controller. A bi−directional level translator adapts the
Output serial C8 signal between the smart card and the external controller. A built−in constant 11 kW
(typical) resistor provides a high impedance state.
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