MC100LVE210
Z
o
= 50
W
Q
Driver
Device
Q
D
Receiver
Device
Z
o
= 50
W
50
W
50
W
D
V
TT
V
TT
= V
CC
− 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device
MC100LVE210FN
MC100LVE210FNG
MC100LVE210FNR2
MC100LVE210FNR2G
Package
PLCC−28
PLCC−28
(Pb−Free)
PLCC−28
PLCC−28
(Pb−Free)
Shipping
†
37 Units / Rail
37 Units / Rail
500 Tape & Reel
500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
− ECL Clock Distribution Techniques
− Designing with PECL (ECL at +5.0 V)
− ECLinPSt I/O SPiCE Modeling Kit
− Metastability and the ECLinPS Family
− Interfacing Between LVDS and ECL
− The ECL Translator Guide
− Odd Number Counters Design
− Marking and Date Codes
− Termination of ECL Logic Devices
− Interfacing with ECLinPS
− AC Characteristics of ECL Devices
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