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CAT24C64WI-GT3 参数 Datasheet PDF下载

CAT24C64WI-GT3图片预览
型号: CAT24C64WI-GT3
PDF下载: 下载PDF文件 查看货源
内容描述: 64 KB I2C CMOS串行EEPROM [64 kb I2C CMOS Serial EEPROM]
分类和应用: 存储内存集成电路光电二极管双倍数据速率PC可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 15 页 / 180 K
品牌: ONSEMI [ ONSEMI ]
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CAT24C64  
READ OPERATIONS  
Immediate Read  
Write sequence by sending data, the Master then creates a  
START condition and broadcasts a Slave address with the  
R/W bit set to ‘1’. The Slave responds with ACK after every  
byte sent by the Master and then sends out data residing at  
the selected address. After receiving the data, the Master  
responds with NoACK and then terminates the session by  
creating a STOP condition on the bus (Figure 11).  
To read data from memory, the Master creates a START  
condition on the bus and then broadcasts a Slave address  
with the R/W bit set to ‘1’. The Slave responds with ACK  
and starts shifting out data residing at the current address.  
After receiving the data, the Master responds with NoACK  
and terminates the session by creating a STOP condition on  
the bus (Figure 10). The Slave then returns to Standby mode.  
Sequential Read  
Selective Read  
If, after receiving data sent by the Slave, the Master  
responds with ACK, then the Slave will continue  
transmitting until the Master responds with NoACK  
followed by STOP (Figure 12). During Sequential Read the  
internal byte address is automatically incremented up to the  
end of memory, where it then wraps around to the beginning  
of memory.  
To read data residing at a specic address, the selected  
address must rst be loaded into the internal address register.  
This is done by starting a Byte Write sequence, whereby the  
Master creates a START condition, then broadcasts a Slave  
address with the R/W bit set to ‘0’ and then sends two  
address bytes to the Slave. Rather than completing the Byte  
N
S
T
A
R
T
O
BUS ACTIVITY:  
MASTER  
S
A T  
C O  
K P  
SLAVE  
ADDRESS  
S
P
A
DATA  
C
SLAVE  
8
BYTE  
K
SCL  
SDA  
9
8th Bit  
DATA OUT  
NO ACK  
STOP  
Figure 10. Immediate Read Sequence and Timing  
N
O
A
C
K
BUS ACTIVITY:  
S
T
A
R
T
S
T
A
S
T
ADDRESS  
BYTE  
ADDRESS  
BYTE  
SLAVE  
SLAVE  
MASTER  
R
T
O
P
ADDRESS  
ADDRESS  
S
S
P
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE  
DATA  
BYTE  
Figure 11. Selective Read Sequence  
N
O
A
C
K
BUS ACTIVITY:  
MASTER  
S
T
A
C
K
A
C
K
A
C
K
SLAVE  
ADDRESS  
O
P
P
A
C
K
SLAVE  
DATA  
BYTE  
n
DATA  
BYTE  
n+1  
DATA  
BYTE  
n+2  
DATA  
BYTE  
n+x  
Figure 12. Sequential Read Sequence  
http://onsemi.com  
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