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CAT1021LE-45TE13 参数 Datasheet PDF下载

CAT1021LE-45TE13图片预览
型号: CAT1021LE-45TE13
PDF下载: 下载PDF文件 查看货源
内容描述: [1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP8, LEAD AND HALOGEN FREE, PLASTIC, DIP-8]
分类和应用: 光电二极管
文件页数/大小: 20 页 / 193 K
品牌: ONSEMI [ ONSEMI ]
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CAT1021, CAT1022, CAT1023  
ACKNOWLEDGE  
After a successful data transfer, each receiving device is  
When a device begins a READ mode it transmits 8 bits of  
data, releases the SDA line and monitors the line for an  
acknowledge. Once it receives this acknowledge, the device  
will continue to transmit data. If no acknowledge is sent by  
the Master, the device terminates data transmission and  
waits for a STOP condition.  
required to generate an acknowledge. The acknowledging  
device pulls down the SDA line during the ninth clock cycle,  
signaling that it received the 8 bits of data.  
All devices respond with an acknowledge after receiving  
a START condition and its slave address. If the device has  
been selected along with a write operation, it responds with  
an acknowledge after receiving each 8bit byte.  
WRITE OPERATIONS  
Byte Write  
Master device transmits the data to be written into the  
addressed memory location. The device acknowledges once  
more and the Master generates the STOP condition. At this  
time, the device begins an internal programming cycle to  
nonvolatile memory. While the cycle is in progress, the  
device will not respond to any request from the Master  
device.  
In the Byte Write mode, the Master device sends the  
START condition and the slave address information (with  
the R/W bit set to zero) to the Slave device. After the Slave  
generates an acknowledge, the Master sends a 8bit address  
that is to be written into the address pointers of the device.  
After receiving another acknowledge from the Slave, the  
SDA  
SCL  
START BIT  
STOP BIT  
Figure 5. Start/Stop Timing  
SCL FROM  
MASTER  
1
8
9
DATA OUTPUT  
FROM TRANSMITTER  
DATA OUTPUT  
FROM RECEIVER  
START  
ACKNOWLEDGE  
Figure 6. Acknowledge Timing  
Default Configuration  
1
0
1
0
0
0
0
R/W  
Figure 7. Slave Address Bits  
http://onsemi.com  
10  
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