74HC595
LOGIC DIAGRAM
SERIAL
DATA
INPUT
A
14
15
1
2
3
SHIFT
REGISTER
4
LATCH
5
6
7
SHIFT 11
CLOCK
10
RESET
LATCH 12
CLOCK
OUTPUT 13
ENABLE
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
PARALLEL
DATA
OUTPUTS
PIN ASSIGNMENT
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
Q
A
A
OUTPUT ENABLE
LATCH CLOCK
SHIFT CLOCK
RESET
SQ
H
9
SQ
H
SERIAL
DATA
OUTPUT
V
CC
= PIN 16
GND = PIN 8
ORDERING INFORMATION
Device
74HC595DR2G
74HC595DTR2G
Package
SOIC−16
(Pb−Free)
TSSOP−16*
Shipping
†
2500 Tape & Reel
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
http://onsemi.com
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