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74HC595DTR2G 参数 Datasheet PDF下载

74HC595DTR2G图片预览
型号: 74HC595DTR2G
PDF下载: 下载PDF文件 查看货源
内容描述: 8位串行输入/串行或并行输出移位锁存具有三态输出寄存器 [8−Bit Serial−Input/Serial or Parallel−Output Shift Register with Latched 3−State Outputs]
分类和应用:
文件页数/大小: 13 页 / 156 K
品牌: ONSEMI [ ON SEMICONDUCTOR ]
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74HC595
8−Bit Serial−Input/Serial or
Parallel−Output Shift
Register with Latched
3−State Outputs
High−Performance Silicon−Gate CMOS
The 74HC595 consists of an 8−bit shift register and an 8−bit D−type
latch with three−state parallel outputs. The shift register accepts serial
data and provides a serial output. The shift register also provides
parallel data to the 8−bit latch. The shift register and latch have
independent clock inputs. This device also has an asynchronous reset
for the shift register.
The HC595 directly interfaces with the SPI serial data port on
CMOS MPUs and MCUs.
Features
http://onsemi.com
MARKING
DIAGRAMS
16
16
1
SOIC−16
D SUFFIX
CASE 751B
1
16
16
1
TSSOP−16
DT SUFFIX
CASE 948F
1
HC
595
ALYW
G
G
HC595G
AWLYWW
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC
Standard No. 7A
ESD Performance: HBM
>
2000 V; Machine Model
>
200 V
Chip Complexity: 328 FETs or 82 Equivalent Gates
Improvements over HC595
Improved Propagation Delays
50% Lower Quiescent Power
Improved Input Noise and Latchup Immunity
These are Pb−Free Devices
HC595 = Device Code
A
= Assembly Location
L, WL
= Wafer Lot
Y, YY
= Year
W, WW = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
©
Semiconductor Components Industries, LLC, 2007
March, 2007
Rev. 1
1
Publication Order Number:
74HC595/D