74HC595
SWITCHING WAVEFORMS
t
r
SHIFT
CLOCK
90%
50%
10%
t
w
1/f
max
t
PLH
OUTPUT
SQ
H
90%
50%
10%
t
TLH
t
THL
t
PHL
t
f
V
CC
GND
OUTPUT
SQ
H
SHIFT
CLOCK
RESET
t
PHL
50%
t
rec
50%
V
CC
GND
50%
t
w
V
CC
GND
Figure 1.
V
CC
GND
t
PLH
90%
Q
A
−Q
H
50%
OUTPUTS 10%
t
TLH
t
THL
t
PHL
OUTPUT
ENABLE
50%
Figure 2.
V
CC
t
PZL
50%
t
PZH
OUTPUT Q
50%
t
PHZ
t
PLZ
10%
90%
GND
HIGH
IMPEDANCE
V
OL
V
OH
HIGH
IMPEDANCE
LATCH
CLOCK
50%
OUTPUT Q
Figure 3.
SHIFT
CLOCK
Figure 4.
V
CC
GND
t
su
LATCH
CLOCK
50%
t
w
V
CC
GND
VALID
SERIAL
INPUT A
SWITCH
CLOCK
50%
t
su
t
h
50%
V
CC
GND
V
CC
GND
50%
Figure 5.
Figure 6.
TEST CIRCUITS
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C
L
*
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kW
CONNECT TO V
CC
WHEN
TESTING t
PLZ
AND t
PZL
.
CONNECT TO GND WHEN
TESTING t
PHZ
AND t
PZH
.
C
L
*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 7.
Figure 8.
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