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74HC595DTR2G 参数 Datasheet PDF下载

74HC595DTR2G图片预览
型号: 74HC595DTR2G
PDF下载: 下载PDF文件 查看货源
内容描述: 8位串行输入/串行或并行输出移位锁存具有三态输出寄存器 [8−Bit Serial−Input/Serial or Parallel−Output Shift Register with Latched 3−State Outputs]
分类和应用:
文件页数/大小: 13 页 / 156 K
品牌: ONSEMI [ ON SEMICONDUCTOR ]
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74HC595
TIMING REQUIREMENTS
(Input t
r
= t
f
= 6.0 ns)
Symbol
t
su
Parameter
Minimum Setup Time, Serial Data Input A to Shift Clock
(Figure 5)
V
CC
(V)
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
Guaranteed Limit
25_C to –55_C
50
40
10
9.0
75
60
15
13
5.0
5.0
5.0
5.0
50
40
10
9.0
60
45
12
10
50
40
10
9.0
50
40
10
9.0
1000
800
500
400
v
85_C
65
50
13
11
95
70
19
16
5.0
5.0
5.0
5.0
65
50
13
11
75
60
15
13
65
50
13
11
65
50
13
11
1000
800
500
400
v
125_C
75
60
15
13
110
80
22
19
5.0
5.0
5.0
5.0
75
60
15
13
90
70
18
15
75
60
15
13
75
60
15
13
1000
800
500
400
Unit
ns
t
su
Minimum Setup Time, Shift Clock to Latch Clock
(Figure 6)
ns
t
h
Minimum Hold Time, Shift Clock to Serial Data Input A
(Figure 5)
ns
t
rec
Minimum Recovery Time, Reset Inactive to Shift Clock
(Figure 2)
ns
t
w
Minimum Pulse Width, Reset
(Figure 2)
ns
t
w
Minimum Pulse Width, Shift Clock
(Figure 1)
ns
t
w
Minimum Pulse Width, Latch Clock
(Figure 6)
ns
t
r
, t
f
Maximum Input Rise and Fall Times
(Figure 1)
ns
http://onsemi.com
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