74HC595
FUNCTION TABLE
Inputs
Serial
Input
A
X
D
X
X
Shift
Clock
X
↑
L, H,
↓
L, H,
↓
Latch
Clock
L, H,
↓
L, H,
↓
L, H,
↓
↑
Output
Enable
L
L
L
L
Shift
Register
Contents
L
D→SR
A
;
SR
N
→SR
N+1
U
U
Resulting Function
Latch
Register
Contents
U
U
U
SR
N
→LR
N
Serial
Output
SQ
H
L
SR
G
→SR
H
U
U
Parallel
Outputs
Q
A
−
Q
H
U
U
U
SR
N
Operation
Reset shift register
Shift data into shift
register
Shift register remains
unchanged
Transfer shift register
contents to latch
register
Latch register remains
unchanged
Enable parallel outputs
Force outputs into high
impedance state
Reset
L
H
H
H
X
X
X
X
X
X
X
X
X
L, H,
↓
X
X
L
L
H
↑
= Low−to−High
↓
= High−to−Low
*
*
*
U
**
**
*
*
*
U
Enabled
Z
SR = shift register contents
LR = latch register contents
D = data (L, H) logic level
U = remains unchanged
* = depends on Reset and Shift Clock inputs
** = depends on Latch Clock input
PIN DESCRIPTIONS
INPUTS
A (Pin 14)
Output Enable (Pin 13)
Serial Data Input. The data on this pin is shifted into the
8−bit serial shift register.
CONTROL INPUTS
Shift Clock (Pin 11)
Active−low Output Enable. A low on this input allows the
data from the latches to be presented at the outputs. A high
on this input forces the outputs (Q
A
−Q
H
) into the
high−impedance state. The serial output is not affected by
this control unit.
OUTPUTS
Q
A
−
Q
H
(Pins 15, 1, 2, 3, 4, 5, 6, 7)
Shift Register Clock Input. A low− to−high transition on
this input causes the data at the Serial Input pin to be shifted
into the 8−bit shift register.
Reset (Pin 10)
Noninverted, 3−state, latch outputs.
SQ
H
(Pin 9)
Active−low, Asynchronous, Shift Register Reset Input. A
low on this pin resets the shift register portion of this device
only. The 8−bit latch is not affected.
Latch Clock (Pin 12)
Noninverted, Serial Data Output. This is the output of the
eighth stage of the 8−bit shift register. This output does not
have three−state capability.
Storage Latch Clock Input. A low−to−high transition on
this input latches the shift register data.
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