BelaSigna 200
6.0 Architecture Overview
6.1 RCore DSP
The RCore is a 16-bit fixed-point, dual-Harvard-architecture DSP. It includes efficient normalize and de-normalize instructions, plus
support for double-precision operations to provide the additional dynamic range needed for many applications. All memory locations in
the system are accessible by the RCore using several addressing modes including indirect and circular modes. The RCore generally
assumes master functionality of the system.
6.1.1. RCore DSP Architecture
Internal Router
DCU
D_AUX_REG0
D_AUX_REG4
EXT3
D_INT_STATUS
D_INT_EBL
D_SYS_CTRL
X
Y
X_Bus
XRAM
MU
PH
PL
LC0
LC1
PCU
REP
X_AGU
R0
PCFG0
PCFG1
PCFG2
R1
R2
R3
CTRL
ALU
ST
Y_Bus
EXP
YRAM
PRAM
Y_AGU
PCFG4
Barrel
Shifter
AH
AE
AL
P_Bus
R4
R5
R6
R7
PCFG5
PCFG6
PC
Limiter
IMM/SIMM
Data registers
Internal Router
Figure 9: RCore Programming Model
The RCore is a single-cycle pipelined multiply-accumulate (MAC) architecture that feeds into a 40-bit accumulator complete with barrel
shifter for fast normalization and de-normalization operations. Program execution is controlled by a sequencer that employs a three-
stage pipeline (FETCH, DECODE, EXECUTE). Furthermore, the RCore incorporates pointer configuration registers for low cycle-count
address generation when accessing the three memories: program memory (PRAM), X data memory (XRAM) and Y data memory
(YRAM).
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